def __init__(self, toolchain="quartus"): AlteraPlatform.__init__(self, "10CL025YU256C8G", _io, toolchain=toolchain)
def __init__(self, id = 0): _device, _io = _variants[id] AlteraPlatform.__init__(self, _device, _io) self.add_platform_command("set_global_assignment -name FAMILY \"Cyclone 10 LP\"")
def __init__(self): AlteraPlatform.__init__(self, "10M50DAF484C7G", _io)
def do_finalize(self, fragment): AlteraPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9 / 50e6)
def __init__(self): AlteraPlatform.__init__(self, "10M50DAF484C7G", _io, toolchain="quartus")
def __init__(self): AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io) self.add_extension(_mister_sdram_module_io)
def __init__(self): AlteraPlatform.__init__(self, "10M50DAF484C7G", _io) self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"") self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF") self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"")
def __init__(self): AlteraPlatform.__init__(self, "EP2C35F484C8", _io)
def __init__(self): AlteraPlatform.__init__(self, "10CL025YU256C8G", _io)
def __init__(self): AlteraPlatform.__init__(self, "EP4CE15F23C8", _io)
def __init__(self): AlteraPlatform.__init__(self, "10CL025YU256I7G", _io) self.add_platform_command( "set_global_assignment -name FAMILY \"Cyclone 10 LP\"")
def __init__(self, toolchain="quartus"): AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io, _connectors, toolchain=toolchain)
def __init__(self, toolchain="quartus"): AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io, toolchain=toolchain) self.add_extension(_mister_sdram_module_io)
def __init__(self, toolchain="quartus"): AlteraPlatform.__init__(self, "EP4CE6E22C8", _io, toolchain=toolchain)
def __init__(self): AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io)
def main(): parser = argparse.ArgumentParser( description="LitePCIe standalone core generator") parser.add_argument("config", help="YAML config file") parser.add_argument("--doc", action="store_true", help="Build documentation") args = parser.parse_args() core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader) # Convert YAML elements to Python/LiteX -------------------------------------------------------- for k, v in core_config.items(): replaces = {"False": False, "True": True, "None": None} for r in replaces.keys(): if v == r: core_config[k] = replaces[r] # Generate core -------------------------------------------------------------------------------- if core_config["phy"] == "C5PCIEPHY": from litex.build.altera import AlteraPlatform from litepcie.phy.c5pciephy import C5PCIEPHY platform = AlteraPlatform("", io=[]) core_config["phy"] = C5PCIEPHY core_config["qword_aligned"] = True core_config["endianness"] = "little" elif core_config["phy"] == "S7PCIEPHY": from litex.build.xilinx import XilinxPlatform from litepcie.phy.s7pciephy import S7PCIEPHY platform = XilinxPlatform(core_config["phy_device"], io=[], toolchain="vivado") core_config["phy"] = S7PCIEPHY core_config["qword_aligned"] = False core_config["endianness"] = "big" elif core_config["phy"] == "USPCIEPHY": from litex.build.xilinx import XilinxPlatform from litepcie.phy.uspciephy import USPCIEPHY platform = XilinxPlatform(core_config["phy_device"], io=[], toolchain="vivado") core_config["phy"] = USPCIEPHY core_config["qword_aligned"] = False core_config["endianness"] = "little" elif core_config["phy"] == "USPPCIEPHY": from litex.build.xilinx import XilinxPlatform from litepcie.phy.uspciephy import USPPCIEPHY platform = XilinxPlatform(core_config["phy_device"], io=[], toolchain="vivado") core_config["phy"] = USPPCIEPHY core_config["qword_aligned"] = False core_config["endianness"] = "little" else: raise ValueError("Unsupported PCIe PHY: {}".format(core_config["phy"])) soc = LitePCIeCore(platform, core_config) builder = Builder(soc, output_dir="build", compile_gateware=False) builder.build(build_name="litepcie_core", regular_comb=True) generate_litepcie_software_headers(soc, "./") if args.doc: soc.generate_documentation("litepcie_core")
def __init__(self): AlteraPlatform.__init__(self, "10CL055YU484A7G", _io)
def __init__(self): AlteraPlatform.__init__(self, "EP4CE6E22C8", _io)
def __init__(self): AlteraPlatform.__init__(self, "EP4CE115F29C7", _io)
def __init__(self): AlteraPlatform.__init__(self, "5CSXFC6D6F31C8", _io)
def __init__(self): AlteraPlatform.__init__(self, "EP4CE22F17C6", _io)
def __init__(self): AlteraPlatform.__init__(self, "EP4CE22F17C6", _io, _connectors)
def __init__(self, toolchain="quartus"): AlteraPlatform.__init__(self, "10CL055YU484A7G", _io, toolchain=toolchain)