def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs): platform = de1soc.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on DE1-SoC", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy=self.sdrphy, module=IS42S16320(sys_clk_freq, "1:1"), l2_cache_size=kwargs.get("l2_size", 8192)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), **kwargs): platform = de1soc.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on DE1-SoC", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy=self.sdrphy, module=IS42S16320(sys_clk_freq, "1:1"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True)
def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = de1soc.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) # ISSI IS42S16320D-7TL sdram_module = IS42S16320(self.clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)