def main(tau=1e-6): print('Running model generator...') # parse command line arguments parser = ArgumentParser() parser.add_argument('-o', '--output', type=str) parser.add_argument('--dt', type=float) args = parser.parse_args() # create the model m = MixedSignalModel('filter', dt=args.dt) m.add_analog_input('v_in') m.add_analog_output('v_out') c = m.make_circuit() gnd = c.make_ground() c.voltage('net_v_in', gnd, m.v_in) c.diode('net_v_in', 'net_v_x', vf=0) c.resistor('net_v_x', 'net_v_out', 1e3) v_out = c.capacitor('net_v_out', gnd, 1e-9, voltage_range=1.5) m.set_this_cycle(m.v_out, v_out) # determine the output filename filename = os.path.join(get_full_path(args.output), f'{m.module_name}.sv') print('Model will be written to: ' + filename) # generate the model m.compile_to_file(VerilogGenerator(), filename)
def main(): dt = 0.1e-6 res = 1e3 cap = 1e-9 m = MixedSignalModel('model', dt=dt) m.add_analog_input('v_in') m.add_analog_output('v_out') c = m.make_circuit() gnd = c.make_ground() c.capacitor('net_v_out', gnd, cap, voltage_range=RangeOf(m.v_out)) c.resistor('net_v_in', 'net_v_out', res) c.voltage('net_v_in', gnd, m.v_in) c.add_eqns(AnalogSignal('net_v_out') == m.v_out) m.compile_and_print(VerilogGenerator())
def main(cap=1e-12, res=600): ctrl = ExampleControl() # define ports m = MixedSignalModel('current_switch', dt=ctrl.dt) m.add_digital_input('ctrl') m.add_analog_input('v_in') m.add_analog_output('v_out') # define the circuit c = m.make_circuit() gnd = c.make_ground() c.switch('net_v_in', 'net_v_out', m.ctrl, r_on=res, r_off=10e3 * res) c.capacitor('net_v_out', gnd, cap, voltage_range=RangeOf(m.v_out)) c.voltage('net_v_in', gnd, m.v_in) c.add_eqns(m.v_out == AnalogSignal('net_v_out')) # write model ctrl.write_model(m)
def main(): dt = 0.1e-6 m = MixedSignalModel('model', dt=dt) m.add_analog_input('v_in') m.add_analog_output('v_out') m.add_digital_input('sw1') m.add_digital_input('sw2') c = m.make_circuit() gnd = c.make_ground() c.voltage('net_v_in', gnd, m.v_in) c.switch('net_v_in', 'net_v_x', m.sw1, r_on=1.0, r_off=2.0) c.switch('net_v_x', gnd, m.sw2, r_on=3.0, r_off=4.0) c.add_eqns( AnalogSignal('net_v_x') == m.v_out ) m.compile_and_print(VerilogGenerator())
def main(): dt = 1e-9 m = MixedSignalModel('model', dt=dt) m.add_analog_input('v_in') m.add_analog_output('v_out') m.add_digital_input('sw1') m.add_digital_input('sw2') c = m.make_circuit() gnd = c.make_ground() c.voltage('net_v_in', gnd, m.v_in) c.switch('net_v_in', 'net_v_x', m.sw1) c.switch('net_v_x', gnd, m.sw2) c.inductor('net_v_in', 'net_v_x', 1, current_range=100) c.add_eqns(AnalogSignal('net_v_x') == m.v_out) m.compile_and_print(VerilogGenerator())