def test_nested_struct(do_test): @bitstruct class inner_struct: foo: Bits32 @bitstruct class struct: bar: Bits32 inner: inner_struct class A(Component): def construct(s): s.in_ = [InPort(struct) for _ in range(2)] a = A() inner = rdt.Struct(inner_struct, {'foo': rdt.Vector(32)}) st = rdt.Struct(struct, {'bar': rdt.Vector(32), 'inner': inner}) a._ref_ports = [ (['clk'], 'clk', rt.Port('input', rdt.Vector(1)), 0), (['in_'], 'in_', rt.Array([2], rt.Port('input', st)), 0), (['reset'], 'reset', rt.Port('input', rdt.Vector(1)), 0), ] a._ref_ports_yosys = [ (['clk'], 'clk', rt.Port('input', rdt.Vector(1)), 0), (['in_[0].bar'], 'in___0__bar', rt.Port('input', rdt.Vector(32)), 0), (['in_[0].inner.foo'], 'in___0__inner__foo', rt.Port('input', rdt.Vector(32)), 0), (['in_[1].bar'], 'in___1__bar', rt.Port('input', rdt.Vector(32)), 0), (['in_[1].inner.foo'], 'in___1__inner__foo', rt.Port('input', rdt.Vector(32)), 0), (['reset'], 'reset', rt.Port('input', rdt.Vector(1)), 0), ] do_test(a)
def test_nested_struct_packed_array_index(do_test): @bitstruct class C: bar: Bits16 @bitstruct class B: foo: Bits32 bar: [C] * 5 class A(Component): def construct(s): s.struct = InPort(B) s.out = OutPort(C) connect(s.struct.bar[1], s.out) a = A() a._ref_name = "A" a._ref_ports = \ """\ port_decls: port_decl: out Port of Struct C port_decl: struct Port of Struct B """ a._ref_wires = "wire_decls:\n" a._ref_consts = "const_decls:\n" a._ref_conns = \ """\ connections: connection: PackedIndex StructAttr CurCompAttr struct bar 1 -> CurCompAttr out """ a._ref_structs = [(rdt.Struct( 'B', { 'foo': rdt.Vector(32), 'bar': rdt.PackedArray([5], rdt.Struct('C', {'bar': rdt.Vector(16)})) }), 'B'), (rdt.Struct('C', {'bar': rdt.Vector(16)}), 'C')] a._ref_src = \ """\ struct C struct B component A ( port_decls: port_decl: out Port of Struct C port_decl: struct Port of Struct B interface_decls: ); const_decls: freevars: wire_decls: component_decls: tmpvars: upblk_srcs: connections: connection: PackedIndex StructAttr CurCompAttr struct bar 1 -> CurCompAttr out endcomponent """ do_test(a)
def test_nested_struct(do_test): class inner_struct(BitStruct): def __init__(s, foo=42): s.foo = Bits32(foo) class struct(BitStruct): def __init__(s, bar=1): s.bar = Bits32(bar) s.inner = inner_struct() class A(Component): def construct(s): s.in_ = [InPort(struct) for _ in range(2)] a = A() inner = rdt.Struct('inner_struct', {'foo': rdt.Vector(32)}, ['foo']) st = rdt.Struct('struct', { 'bar': rdt.Vector(32), 'inner': inner }, ['bar', 'inner']) a._ref_ports = [('clk', rt.Port('input', rdt.Vector(1))), ('in_', rt.Array([2], rt.Port('input', st))), ('reset', rt.Port('input', rdt.Vector(1)))] a._ref_ports_yosys = [ ('clk', rt.Port('input', rdt.Vector(1))), ('in___0__bar', rt.Port('input', rdt.Vector(32))), ('in___0__inner__foo', rt.Port('input', rdt.Vector(32))), ('in___1__bar', rt.Port('input', rdt.Vector(32))), ('in___1__inner__foo', rt.Port('input', rdt.Vector(32))), ('reset', rt.Port('input', rdt.Vector(1))) ] do_test(a)
def test_nested_struct_packed_array_port_decl(do_test): class C(BitStruct): def __init__(s, bar=42): s.bar = Bits16(bar) class B(BitStruct): def __init__(s, foo=0, bar=42): s.foo = Bits32(foo) s.bar = [C() for _ in range(5)] class A(Component): def construct(s): s.struct = InPort(B) a = A() a._ref_name = "A" a._ref_ports = \ """\ port_decls: port_decl: struct Port of Struct B """ a._ref_wires = "wire_decls:\n" a._ref_consts = "const_decls:\n" a._ref_conns = "connections:\n" a._ref_structs = [(rdt.Struct( 'B', { 'foo': rdt.Vector(32), 'bar': rdt.PackedArray([5], rdt.Struct('C', {'bar': rdt.Vector(16)}, ['bar'])) }, ['bar', 'foo']), 'B'), (rdt.Struct('C', {'bar': rdt.Vector(16)}, ['bar']), 'C')] a._ref_src = \ """\ struct C struct B component A ( port_decls: port_decl: struct Port of Struct B interface_decls: ); const_decls: freevars: wire_decls: component_decls: tmpvars: upblk_srcs: connections: endcomponent """ do_test(a)
def test_nested_struct_port_decl(do_test): @bitstruct class C: bar: Bits16 @bitstruct class B: foo: Bits32 bar: C class A(Component): def construct(s): s.struct = InPort(B) a = A() a._ref_name = "A" a._ref_ports = \ """\ port_decls: port_decl: struct Port of Struct B """ a._ref_wires = "wire_decls:\n" a._ref_consts = "const_decls:\n" a._ref_conns = "connections:\n" a._ref_structs = [(rdt.Struct( 'B', { 'foo': rdt.Vector(32), 'bar': rdt.Struct('C', {'bar': rdt.Vector(16)}) }, ), 'B'), (rdt.Struct('C', {'bar': rdt.Vector(16)}), 'C')] a._ref_src = \ """\ struct C struct B component A ( port_decls: port_decl: struct Port of Struct B interface_decls: ); const_decls: freevars: wire_decls: component_decls: tmpvars: upblk_srcs: connections: endcomponent """ do_test(a)
def test_packed_array_port_array(do_test): @bitstruct class struct: bar: Bits32 foo: [[Bits32] * 2] * 3 class A(Component): def construct(s): s.in_ = [InPort(struct) for _ in range(2)] a = A() foo = rdt.PackedArray([3, 2], rdt.Vector(32)) st = rdt.Struct('struct', {'bar': rdt.Vector(32), 'foo': foo}) a._ref_ports = [('clk', rt.Port('input', rdt.Vector(1))), ('in_', rt.Array([2], rt.Port('input', st))), ('reset', rt.Port('input', rdt.Vector(1)))] a._ref_ports_yosys = [ ('clk', rt.Port('input', rdt.Vector(1))), ('in___0__bar', rt.Port('input', rdt.Vector(32))), ('in___0__foo__0__0', rt.Port('input', rdt.Vector(32))), ('in___0__foo__0__1', rt.Port('input', rdt.Vector(32))), ('in___0__foo__1__0', rt.Port('input', rdt.Vector(32))), ('in___0__foo__1__1', rt.Port('input', rdt.Vector(32))), ('in___0__foo__2__0', rt.Port('input', rdt.Vector(32))), ('in___0__foo__2__1', rt.Port('input', rdt.Vector(32))), ('in___1__bar', rt.Port('input', rdt.Vector(32))), ('in___1__foo__0__0', rt.Port('input', rdt.Vector(32))), ('in___1__foo__0__1', rt.Port('input', rdt.Vector(32))), ('in___1__foo__1__0', rt.Port('input', rdt.Vector(32))), ('in___1__foo__1__1', rt.Port('input', rdt.Vector(32))), ('in___1__foo__2__0', rt.Port('input', rdt.Vector(32))), ('in___1__foo__2__1', rt.Port('input', rdt.Vector(32))), ('reset', rt.Port('input', rdt.Vector(1))) ] do_test(a)
def test_struct_const_structural(do_test): class B(BitStruct): fields = [('foo', Bits32)] def __init__(s, foo=42): s.foo = Bits32(foo) class A(Component): def construct(s): s.in_ = B() s.out = OutPort(Bits32) connect(s.out, s.in_.foo) a = A() a._ref_structs = [ ( rdt.Struct( 'B', {'foo':rdt.Vector(32)}, ['foo'] ), \ """\ typedef struct packed { logic [31:0] foo; } B; """ ) ] a._ref_ports = { a : \ """\ input logic [0:0] clk, output logic [31:0] out, input logic [0:0] reset\ """ } a._ref_wires = {a: ""} a._ref_conns = { a : \ """\ assign out = 32'd42;\ """ } # Yosys backend test reference output a._ref_ports_port_yosys = a._ref_ports a._ref_ports_wire_yosys = {a: ""} a._ref_ports_conn_yosys = {a: ""} a._ref_wires_yosys = a._ref_wires a._ref_conns_yosys = a._ref_conns # TestVectorSimulator properties def tv_in(m, tv): pass def tv_out(m, tv): assert m.out == Bits32(tv[0]) a._test_vectors = [ [42], ] a._tv_in, a._tv_out = tv_in, tv_out do_test(a)
def test_struct_wire_decl(do_test): @bitstruct class B: foo: Bits32 bar: Bits16 class A(Component): def construct(s): s.struct = Wire(B) @s.update def upblk(): s.struct.foo = 0 s.struct.bar = Bits16(42) a = A() a._ref_name = "A" a._ref_ports = "port_decls:\n" a._ref_wires = \ """\ wire_decls: wire_decl: struct Wire of Struct B """ a._ref_consts = "const_decls:\n" a._ref_conns = "connections:\n" a._ref_structs = [(rdt.Struct('B', { 'foo': rdt.Vector(32), 'bar': rdt.Vector(16) }), 'B')] a._ref_src = \ """\ struct B component A ( port_decls: interface_decls: ); const_decls: freevars: wire_decls: wire_decl: struct Wire of Struct B component_decls: tmpvars: upblk_srcs: upblk_src: upblk connections: endcomponent """ do_test(a)
def test_struct_packed_array_port_decl(do_test): @bitstruct class B: foo: [Bits32] * 5 bar: Bits16 class A(Component): def construct(s): s.struct = InPort(B) a = A() a._ref_name = "A" a._ref_ports = \ """\ port_decls: port_decl: struct Port of Struct B """ a._ref_wires = "wire_decls:\n" a._ref_consts = "const_decls:\n" a._ref_conns = "connections:\n" a._ref_structs = [ (rdt.Struct('B', { 'foo': rdt.PackedArray([5], rdt.Vector(32)), 'bar': rdt.Vector(16) }), 'B') ] a._ref_src = \ """\ struct B component A ( port_decls: port_decl: struct Port of Struct B interface_decls: ); const_decls: freevars: wire_decls: component_decls: tmpvars: upblk_srcs: connections: endcomponent """ do_test(a)
def test_struct_port_array(do_test): @bitstruct class B: foo: Bits32 bar: Bits16 class A(Component): def construct(s): s.struct = [InPort(B) for _ in range(5)] a = A() a._ref_name = "A" a._ref_ports = \ """\ port_decls: port_decl: struct Array[5] of Port """ a._ref_wires = "wire_decls:\n" a._ref_consts = "const_decls:\n" a._ref_conns = "connections:\n" a._ref_structs = [(rdt.Struct('B', { 'foo': rdt.Vector(32), 'bar': rdt.Vector(16) }), 'B')] a._ref_src = \ """\ struct B component A ( port_decls: port_decl: struct Array[5] of Port interface_decls: ); const_decls: freevars: wire_decls: component_decls: tmpvars: upblk_srcs: connections: endcomponent """ do_test(a)
def test_struct_const_decl(do_test): @bitstruct class B: foo: Bits32 bar: Bits16 class A(Component): def construct(s): s.struct = B() a = A() a._ref_name = "A" a._ref_ports = "port_decls:\n" a._ref_wires = "wire_decls:\n" a._ref_consts = \ """\ const_decls: const_decl: struct Const of Struct B """ a._ref_conns = "connections:\n" a._ref_structs = [(rdt.Struct('B', { 'foo': rdt.Vector(32), 'bar': rdt.Vector(16) }), 'B')] a._ref_src = \ """\ struct B component A ( port_decls: interface_decls: ); const_decls: const_decl: struct Const of Struct B freevars: wire_decls: component_decls: tmpvars: upblk_srcs: connections: endcomponent """ do_test(a)
def test_struct_port_array(do_test): class B(BitStruct): def __init__(s, foo=0, bar=42): s.foo = Bits32(foo) s.bar = Bits16(bar) class A(Component): def construct(s): s.struct = [InPort(B) for _ in range(5)] a = A() a._ref_name = "A" a._ref_ports = \ """\ port_decls: port_decl: struct Array[5] of Port """ a._ref_wires = "wire_decls:\n" a._ref_consts = "const_decls:\n" a._ref_conns = "connections:\n" a._ref_structs = [(rdt.Struct('B', { 'foo': rdt.Vector(32), 'bar': rdt.Vector(16) }, ['bar', 'foo']), 'B')] a._ref_src = \ """\ struct B component A ( port_decls: port_decl: struct Array[5] of Port interface_decls: ); const_decls: freevars: wire_decls: component_decls: tmpvars: upblk_srcs: connections: endcomponent """ do_test(a)
def test_struct_port_single(do_test): @bitstruct class struct: bar: Bits32 foo: Bits32 class A(Component): def construct(s): s.in_ = InPort(struct) a = A() st = rdt.Struct('struct', {'bar': rdt.Vector(32), 'foo': rdt.Vector(32)}) a._ref_ports = [('clk', rt.Port('input', rdt.Vector(1))), ('in_', rt.Port('input', st)), ('reset', rt.Port('input', rdt.Vector(1)))] a._ref_ports_yosys = [('clk', rt.Port('input', rdt.Vector(1))), ('in___bar', rt.Port('input', rdt.Vector(32))), ('in___foo', rt.Port('input', rdt.Vector(32))), ('reset', rt.Port('input', rdt.Vector(1)))] do_test(a)
def test_packed_array_port_array(do_test): class struct(BitStruct): def __init__(s, bar=1, foo=42): s.bar = Bits32(bar) s.foo = [[Bits32(foo) for _ in range(2)] for _ in range(3)] class A(Component): def construct(s): s.in_ = [InPort(struct) for _ in range(2)] a = A() foo = rdt.PackedArray([3, 2], rdt.Vector(32)) st = rdt.Struct('struct', { 'bar': rdt.Vector(32), 'foo': foo }, ['bar', 'foo']) a._ref_ports = [('clk', rt.Port('input', rdt.Vector(1))), ('in_', rt.Array([2], rt.Port('input', st))), ('reset', rt.Port('input', rdt.Vector(1)))] a._ref_ports_yosys = [ ('clk', rt.Port('input', rdt.Vector(1))), ('in___0__bar', rt.Port('input', rdt.Vector(32))), ('in___0__foo__0__0', rt.Port('input', rdt.Vector(32))), ('in___0__foo__0__1', rt.Port('input', rdt.Vector(32))), ('in___0__foo__1__0', rt.Port('input', rdt.Vector(32))), ('in___0__foo__1__1', rt.Port('input', rdt.Vector(32))), ('in___0__foo__2__0', rt.Port('input', rdt.Vector(32))), ('in___0__foo__2__1', rt.Port('input', rdt.Vector(32))), ('in___1__bar', rt.Port('input', rdt.Vector(32))), ('in___1__foo__0__0', rt.Port('input', rdt.Vector(32))), ('in___1__foo__0__1', rt.Port('input', rdt.Vector(32))), ('in___1__foo__1__0', rt.Port('input', rdt.Vector(32))), ('in___1__foo__1__1', rt.Port('input', rdt.Vector(32))), ('in___1__foo__2__0', rt.Port('input', rdt.Vector(32))), ('in___1__foo__2__1', rt.Port('input', rdt.Vector(32))), ('reset', rt.Port('input', rdt.Vector(1))) ] do_test(a)
def test_struct_port_single(do_test): class struct(BitStruct): def __init__(s, bar=1, foo=42): s.bar = Bits32(bar) s.foo = Bits32(foo) class A(Component): def construct(s): s.in_ = InPort(struct) a = A() st = rdt.Struct('struct', { 'bar': rdt.Vector(32), 'foo': rdt.Vector(32) }, ['bar', 'foo']) a._ref_ports = [('clk', rt.Port('input', rdt.Vector(1))), ('in_', rt.Port('input', st)), ('reset', rt.Port('input', rdt.Vector(1)))] a._ref_ports_yosys = [('clk', rt.Port('input', rdt.Vector(1))), ('in___bar', rt.Port('input', rdt.Vector(32))), ('in___foo', rt.Port('input', rdt.Vector(32))), ('reset', rt.Port('input', rdt.Vector(1)))] do_test(a)
( port_decls: port_decl: in_ Port of Struct Bits32Foo__foo_32 interface_decls: ); const_decls: freevars: wire_decls: component_decls: tmpvars: upblk_srcs: connections: endcomponent ''', 'REF_STRUCT', [(rdt.Struct(Bits32Foo, {'foo': rdt.Vector(32)}), 'Bits32Foo__foo_32')]) CaseStructWireDrivenComp = set_attributes( CaseStructWireDrivenComp, 'REF_NAME', 'DUT', 'REF_PORT', 'port_decls:\n', 'REF_WIRE', '''\ wire_decls: wire_decl: foo Wire of Struct Bits32Foo__foo_32 ''', 'REF_CONST', 'const_decls:\n', 'REF_CONN', 'connections:\n', 'REF_SRC', '''\ struct Bits32Foo__foo_32 component DUT ( port_decls: interface_decls: ); const_decls:
def test_nested_struct_port(do_test): @bitstruct class C: bar: Bits32 @bitstruct class B: c: C foo: Bits32 class A(Component): def construct(s): s.in_ = InPort(B) s.out_foo = OutPort(Bits32) s.out_bar = OutPort(Bits32) connect(s.out_foo, s.in_.foo) connect(s.out_bar, s.in_.c.bar) a = A() _C = rdt.Struct('C', {'bar': rdt.Vector(32)}) a._ref_structs = [ ( _C, \ """\ typedef struct packed { logic [31:0] bar; } C; """ ), ( rdt.Struct( 'B', {'c':_C, 'foo':rdt.Vector(32)} ), \ """\ typedef struct packed { C c; logic [31:0] foo; } B; """ ) ] a._ref_ports = { a : \ """\ input logic [0:0] clk, input B in_, output logic [31:0] out_bar, output logic [31:0] out_foo, input logic [0:0] reset\ """ } a._ref_wires = {a: ""} a._ref_conns = { a : \ """\ assign out_foo = in_.foo; assign out_bar = in_.c.bar;\ """ } # Yosys backend test reference output a._ref_ports_port_yosys = { a : \ """\ input logic [0:0] clk, input logic [31:0] in___c__bar, input logic [31:0] in___foo, output logic [31:0] out_bar, output logic [31:0] out_foo, input logic [0:0] reset\ """ } a._ref_ports_wire_yosys = { a : \ """\ logic [31:0] in___c; logic [63:0] in_;\ """ } a._ref_ports_conn_yosys = { a : \ """\ assign in___c[31:0] = in___c__bar; assign in_[63:32] = in___c__bar; assign in_[31:0] = in___foo;\ """ } a._ref_wires_yosys = a._ref_wires a._ref_conns_yosys = { a : \ """\ assign out_foo = in___foo; assign out_bar = in___c__bar;\ """ } # TestVectorSimulator properties def tv_in(m, tv): m.in_ = tv[0] def tv_out(m, tv): assert m.out_foo == Bits32(tv[1]) assert m.out_bar == Bits32(tv[2]) a._test_vectors = [ [B(), 0, 0], [B(C(2), 1), 1, 2], [B(C(-2), -1), -1, -2], [B(C(-3), -2), -2, -3], [B(C(25), 24), 24, 25], ] a._tv_in, a._tv_out = tv_in, tv_out do_test(a)
def test_nested_struct_port(do_test): class C(BitStruct): def __init__(s, bar=1): s.bar = Bits32(bar) class B(BitStruct): def __init__(s, foo=42): s.foo = Bits32(foo) s.c = C() class A(Component): def construct(s): s.in_ = InPort(B) s.out_foo = OutPort(Bits32) s.out_bar = OutPort(Bits32) connect(s.out_foo, s.in_.foo) connect(s.out_bar, s.in_.c.bar) a = A() _C = rdt.Struct('C', {'bar': rdt.Vector(32)}, ['bar']) a._ref_structs = [ ( _C, \ """\ typedef struct packed { logic [31:0] bar; } C; """ ), ( rdt.Struct( 'B', {'c':_C, 'foo':rdt.Vector(32)}, ['c', 'foo'] ), \ """\ typedef struct packed { C c; logic [31:0] foo; } B; """ ) ] a._ref_ports = { a : \ """\ input logic [0:0] clk, input B in_, output logic [31:0] out_bar, output logic [31:0] out_foo, input logic [0:0] reset\ """ } a._ref_wires = {a: ""} a._ref_conns = { a : \ """\ assign out_foo = in_.foo; assign out_bar = in_.c.bar;\ """ } # Yosys backend test reference output a._ref_ports_port_yosys = { a : \ """\ input logic [0:0] clk, input logic [31:0] in___c__bar, input logic [31:0] in___foo, output logic [31:0] out_bar, output logic [31:0] out_foo, input logic [0:0] reset\ """ } a._ref_ports_wire_yosys = { a : \ """\ logic [31:0] in___c; logic [63:0] in_;\ """ } a._ref_ports_conn_yosys = { a : \ """\ assign in___c[31:0] = in___c__bar; assign in_[63:32] = in___c__bar; assign in_[31:0] = in___foo;\ """ } a._ref_wires_yosys = a._ref_wires a._ref_conns_yosys = { a : \ """\ assign out_foo = in___foo; assign out_bar = in___c__bar;\ """ } # TestVectorSimulator properties def tv_in(m, tv): m.in_ = tv[0] def tv_out(m, tv): assert m.out_foo == Bits32(tv[1]) assert m.out_bar == Bits32(tv[2]) a._test_vectors = [ [B(), 42, 1], [B(1), 1, 1], [B(-1), -1, 1], [B(-2), -2, 1], [B(24), 24, 1], ] a._tv_in, a._tv_out = tv_in, tv_out do_test(a)
port_decls: port_decl: in_ Port of Struct Bits32Foo__foo_32 interface_decls: ); const_decls: freevars: wire_decls: component_decls: tmpvars: upblk_srcs: connections: endcomponent ''', 'REF_STRUCT', [(rdt.Struct('Bits32Foo', {'foo':rdt.Vector(32)}), 'Bits32Foo__foo_32')] ) CaseStructWireDrivenComp = set_attributes( CaseStructWireDrivenComp, 'REF_NAME', 'DUT', 'REF_PORT', 'port_decls:\n', 'REF_WIRE', '''\ wire_decls: wire_decl: foo Wire of Struct Bits32Foo__foo_32 ''', 'REF_CONST', 'const_decls:\n', 'REF_CONN',
( port_decls: port_decl: in_ Port of Struct Bits32Foo interface_decls: ); const_decls: freevars: wire_decls: component_decls: tmpvars: upblk_srcs: connections: endcomponent ''', 'REF_STRUCT', [(rdt.Struct('Bits32Foo', {'foo': rdt.Vector(32)}), 'Bits32Foo')]) CaseStructWireDrivenComp = set_attributes( CaseStructWireDrivenComp, 'REF_NAME', 'DUT', 'REF_PORT', 'port_decls:\n', 'REF_WIRE', '''\ wire_decls: wire_decl: foo Wire of Struct Bits32Foo ''', 'REF_CONST', 'const_decls:\n', 'REF_CONN', 'connections:\n', 'REF_SRC', '''\ struct Bits32Foo component DUT ( port_decls: interface_decls: ); const_decls:
def test_packed_array(do_test): class B(BitStruct): def __init__(s, foo=42): s.foo = [Bits32(foo) for _ in range(2)] class A(Component): def construct(s): s.in_ = InPort(B) s.out = [OutPort(Bits32) for _ in range(2)] connect(s.out[0], s.in_.foo[0]) connect(s.out[1], s.in_.foo[1]) a = A() _foo = rdt.PackedArray([2], rdt.Vector(32)) a._ref_structs = [ ( rdt.Struct( 'B', {'foo':_foo}, ['foo'] ), \ """\ typedef struct packed { logic [1:0][31:0] foo; } B; """ ) ] a._ref_ports = { a : \ """\ input logic [0:0] clk, input B in_, output logic [31:0] out [0:1], input logic [0:0] reset\ """ } a._ref_wires = {a: ""} a._ref_conns = { a : \ """\ assign out[0] = in_.foo[0]; assign out[1] = in_.foo[1];\ """ } # Yosys backend test reference output a._ref_ports_port_yosys = { a : \ """\ input logic [0:0] clk, input logic [31:0] in___foo__0, input logic [31:0] in___foo__1, output logic [31:0] out__0, output logic [31:0] out__1, input logic [0:0] reset\ """ } a._ref_ports_wire_yosys = { a : \ """\ logic [31:0] in___foo [0:1]; logic [63:0] in_; logic [31:0] out [0:1];\ """ } a._ref_ports_conn_yosys = { a : \ """\ assign in___foo[0] = in___foo__0; assign in___foo[1] = in___foo__1; assign in_[63:32] = in___foo__1; assign in_[31:0] = in___foo__0; assign out__0 = out[0]; assign out__1 = out[1];\ """ } a._ref_wires_yosys = a._ref_wires a._ref_conns_yosys = { a : \ """\ assign out[0] = in___foo[0]; assign out[1] = in___foo[1];\ """ } # TestVectorSimulator properties def tv_in(m, tv): m.in_ = tv[0] def tv_out(m, tv): assert m.out[0] == Bits32(tv[1]) assert m.out[1] == Bits32(tv[2]) a._test_vectors = [ [B(), 42, 42], [B(1), 1, 1], [B(-1), -1, -1], [B(-2), -2, -2], [B(24), 24, 24], ] a._tv_in, a._tv_out = tv_in, tv_out do_test(a)
def test_struct_packed_array(do_test): class C(BitStruct): def __init__(s, bar=1): s.bar = Bits32(bar) class B(BitStruct): def __init__(s): s.c = [C() for _ in range(2)] class A(Component): def construct(s): s.in_ = InPort(B) s.out = [OutPort(Bits32) for _ in range(2)] connect(s.out[0], s.in_.c[0].bar) connect(s.out[1], s.in_.c[1].bar) a = A() _C = rdt.Struct('C', {'bar': rdt.Vector(32)}, ['bar']) a._ref_structs = [ ( _C, \ """\ typedef struct packed { logic [31:0] bar; } C; """ ), ( rdt.Struct( 'B', {'c':rdt.PackedArray([2], _C)}, ['c'] ), \ """\ typedef struct packed { C [1:0] c; } B; """ ) ] a._ref_ports = { a : \ """\ input logic [0:0] clk, input B in_, output logic [31:0] out [0:1], input logic [0:0] reset\ """ } a._ref_wires = {a: ""} a._ref_conns = { a : \ """\ assign out[0] = in_.c[0].bar; assign out[1] = in_.c[1].bar;\ """ } # Yosys backend test reference output a._ref_ports_port_yosys = { a : \ """\ input logic [0:0] clk, input logic [31:0] in___c__0__bar, input logic [31:0] in___c__1__bar, output logic [31:0] out__0, output logic [31:0] out__1, input logic [0:0] reset\ """ } a._ref_ports_wire_yosys = { a : \ """\ logic [31:0] in___c__bar [0:1]; logic [31:0] in___c [0:1]; logic [63:0] in_; logic [31:0] out [0:1];\ """ } a._ref_ports_conn_yosys = { a : \ """\ assign in___c__bar[0] = in___c__0__bar; assign in___c[0][31:0] = in___c__0__bar; assign in___c__bar[1] = in___c__1__bar; assign in___c[1][31:0] = in___c__1__bar; assign in_[63:32] = in___c__1__bar; assign in_[31:0] = in___c__0__bar; assign out__0 = out[0]; assign out__1 = out[1];\ """ } a._ref_wires_yosys = a._ref_wires a._ref_conns_yosys = { a : \ """\ assign out[0] = in___c__bar[0]; assign out[1] = in___c__bar[1];\ """ } # TestVectorSimulator properties def tv_in(m, tv): m.in_ = tv[0] def tv_out(m, tv): assert m.out[0] == Bits32(tv[1]) assert m.out[1] == Bits32(tv[2]) a._test_vectors = [ [B(), 1, 1], ] a._tv_in, a._tv_out = tv_in, tv_out do_test(a)
def test_struct_port(do_test): class B(BitStruct): def __init__(s, foo=42): s.foo = Bits32(foo) class A(Component): def construct(s): s.in_ = InPort(B) s.out = OutPort(Bits32) connect(s.out, s.in_.foo) a = A() a._ref_structs = [ ( rdt.Struct( 'B', {'foo':rdt.Vector(32)}, ['foo'] ), \ """\ typedef struct packed { logic [31:0] foo; } B; """ ) ] a._ref_ports = { a : \ """\ input logic [0:0] clk, input B in_, output logic [31:0] out, input logic [0:0] reset\ """ } a._ref_wires = {a: ""} a._ref_conns = { a : \ """\ assign out = in_.foo;\ """ } # Yosys backend test reference output a._ref_ports_port_yosys = { a : \ """\ input logic [0:0] clk, input logic [31:0] in___foo, output logic [31:0] out, input logic [0:0] reset\ """ } a._ref_ports_wire_yosys = { a : \ """\ logic [31:0] in_;\ """ } a._ref_ports_conn_yosys = { a : \ """\ assign in_[31:0] = in___foo;\ """ } a._ref_wires_yosys = a._ref_wires a._ref_conns_yosys = { a : \ """\ assign out = in___foo;\ """ } # TestVectorSimulator properties def tv_in(m, tv): m.in_ = tv[0] def tv_out(m, tv): assert m.out == Bits32(tv[1]) a._test_vectors = [ [B(), 42], [B(0), 0], [B(-1), -1], [B(-2), -2], [B(24), 24], ] a._tv_in, a._tv_out = tv_in, tv_out do_test(a)