コード例 #1
0
ファイル: test_fastsimulation.py プロジェクト: LinChai/PyRTL
    def test_function_RomBlock(self):
        def rom_data_function(add):
            return int((add + 5) / 2)

        pyrtl.reset_working_block()
        self.bitwidth = 4
        self.addrwidth = 4
        self.output1 = pyrtl.Output(self.bitwidth, "o1")
        self.output2 = pyrtl.Output(self.bitwidth, "o2")
        self.read_addr1 = pyrtl.Input(self.addrwidth)
        self.read_addr2 = pyrtl.Input(self.addrwidth)
        self.rom = pyrtl.RomBlock(bitwidth=self.bitwidth,
                                  addrwidth=self.addrwidth,
                                  name='rom',
                                  romdata=rom_data_function)
        self.output1 <<= self.rom[self.read_addr1]
        self.output2 <<= self.rom[self.read_addr2]
        # build the actual simulation environment
        self.sim_trace = pyrtl.SimulationTrace()
        self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)

        input_signals = {}
        for i in range(0, 5):
            input_signals[i] = {self.read_addr1: i, self.read_addr2: 2 * i}
            self.sim.step(input_signals[i])

        exp_out = self.generate_expected_output(
            (("o1", lambda x: rom_data_function(x)),
             ("o2", lambda x: rom_data_function(2 * x))), 6)
        self.compareIO(self.sim_trace, exp_out)
コード例 #2
0
ファイル: test_examples.py プロジェクト: LinChai/PyRTL
def example_t(file):
    print("testing file: " + file)
    pyrtl.reset_working_block()
    try:
        output = subprocess.check_output(['python', file])
    except subprocess.CalledProcessError as e:
        raise e
コード例 #3
0
ファイル: test_fastsimulation.py プロジェクト: LinChai/PyRTL
    def test_function_RomBlock(self):

        def rom_data_function(add):
            return int((add + 5)/2)

        pyrtl.reset_working_block()
        self.bitwidth = 4
        self.addrwidth = 4
        self.output1 = pyrtl.Output(self.bitwidth, "o1")
        self.output2 = pyrtl.Output(self.bitwidth, "o2")
        self.read_addr1 = pyrtl.Input(self.addrwidth)
        self.read_addr2 = pyrtl.Input(self.addrwidth)
        self.rom = pyrtl.RomBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
                                  name='rom', romdata=rom_data_function)
        self.output1 <<= self.rom[self.read_addr1]
        self.output2 <<= self.rom[self.read_addr2]
        # build the actual simulation environment
        self.sim_trace = pyrtl.SimulationTrace()
        self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)

        input_signals = {}
        for i in range(0, 5):
            input_signals[i] = {self.read_addr1: i, self.read_addr2: 2*i}
            self.sim.step(input_signals[i])

        exp_out = self.generate_expected_output((("o1", lambda x: rom_data_function(x)),
                                                 ("o2", lambda x: rom_data_function(2*x))), 6)
        self.compareIO(self.sim_trace, exp_out)
コード例 #4
0
ファイル: test_simulation.py プロジェクト: UCSBarchlab/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     bitwidth = 3
     self.r = pyrtl.Register(bitwidth=bitwidth, name='r')
     self.result = _basic_add(self.r,
                              pyrtl.Const(1).zero_extended(bitwidth))
     self.r.next <<= self.result
コード例 #5
0
def example_t(file):
    print("testing file: " + file)
    pyrtl.reset_working_block()
    try:
        output = subprocess.check_output(['python', file])
    except subprocess.CalledProcessError as e:
        raise e
コード例 #6
0
ファイル: test_fastsimulation.py プロジェクト: LinChai/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     bitwidth = 3
     self.r = pyrtl.Register(bitwidth=bitwidth, name='r')
     self.sum, self.cout = generate_full_adder(
         self.r,
         pyrtl.Const(1).zero_extended(bitwidth))
     self.r.next <<= self.sum
コード例 #7
0
 def setUp(self):
     pyrtl.reset_working_block()
     self.bitwidth = 3
     self.addrwidth = 5
     self.output1 = pyrtl.Output(self.bitwidth, "output1")
     self.in1 = pyrtl.Input(self.addrwidth, name='mem_write_address')
     self.in2 = pyrtl.Input(self.addrwidth, name='mem_write_address')
     self.memory = pyrtl.RomBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
                                  name='self.memory', romdata=self.data, max_read_ports=None)
コード例 #8
0
 def setUp(self):
     pyrtl.reset_working_block()
     self.bitwidth = 3
     self.addrwidth = 5
     self.output1 = pyrtl.Output(self.bitwidth, "output1")
     self.mem_read_address1 = pyrtl.Input(self.addrwidth, name='mem_read_address1')
     self.mem_read_address2 = pyrtl.Input(self.addrwidth, name='mem_read_address2')
     self.mem_write_address = pyrtl.Input(self.addrwidth, name='mem_write_address')
     self.mem_write_data = pyrtl.Input(self.bitwidth, name='mem_write_data')
コード例 #9
0
 def test_undriven_net(self):
     w = pyrtl.WireVector(name='testwire', bitwidth=3)
     self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)
     pyrtl.reset_working_block()
     r = pyrtl.Register(3)
     self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)
     pyrtl.reset_working_block()
     o = pyrtl.Output(3)
     self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)
コード例 #10
0
ファイル: test_simulation.py プロジェクト: UCSBarchlab/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     self.i = pyrtl.Input(bitwidth=3)
     self.r1 = pyrtl.Register(name='r1', bitwidth=3)
     self.r2 = pyrtl.Register(name='r2', bitwidth=3)
     self.o = pyrtl.Output(name='o', bitwidth=3)
     self.r1.next <<= self.i
     self.r2.next <<= self.r1
     self.o <<= self.r2
コード例 #11
0
 def setUp(self):
     pyrtl.reset_working_block()
     # test with '0101' in binary, which should be
     # 5 for an unsigned comparison and should be
     # 5 for an signed comparison
     self.c = pyrtl.Const(0b101, bitwidth=4)
     self.r = pyrtl.Register(bitwidth=4)
     self.o = pyrtl.Output(bitwidth=1, name='o')
     self.r.next <<= self.r + 1
コード例 #12
0
    def test_complete_adders(self):
        for bitwidth in range(9, 10):
            r = pyrtl.Register(bitwidth=bitwidth, name='r')
            const_one = pyrtl.Const(1)
            addby = const_one.zero_extended(bitwidth)
            sum, cout = generate_full_adder(r, addby)
            r.next <<= sum

            self.assertTrue(isinstance(r, pyrtl.Register))
            self.assertTrue(isinstance(cout, pyrtl.WireVector))
            pyrtl.reset_working_block()
コード例 #13
0
    def test_minus_sim_overflow(self):
        pyrtl.reset_working_block()
        i = pyrtl.Input(8, 'i')
        o = pyrtl.Output(name='o')
        o <<= i - 1

        tracer = pyrtl.SimulationTrace()
        sim = self.sim(tracer=tracer)
        sim.step({i: 1})
        sim.step({i: 0})
        self.assertEqual(tracer.trace['o'], [0, 0x1ff])
コード例 #14
0
 def setUp(self):
     pyrtl.reset_working_block()
     in1 = pyrtl.Input(4, "in1")
     in2 = pyrtl.Input(4, "in2")
     out1 = pyrtl.Output(4, "out1")
     out1 <<= (in1 ^ in2) + pyrtl.Const(1)
     out2 = pyrtl.Output(4, "out2")
     out2 <<= in1 | in2
     self.inputs = {
         'in1': [0, 1, 3, 15, 14],
         'in2': [6, 6, 6, 6, 6],
     }
コード例 #15
0
ファイル: test_fastsimulation.py プロジェクト: LinChai/PyRTL
    def setUp(self):
        pyrtl.reset_working_block()
        bitwidth = 3
        self.a = pyrtl.Input(bitwidth=bitwidth)
        self.b = pyrtl.Input(bitwidth=bitwidth)
        self.sel = pyrtl.Input(bitwidth=1)
        self.muxout = pyrtl.Output(bitwidth=bitwidth, name='muxout')
        self.muxout <<= generate_full_mux(self.a, self.b, self.sel)

        # build the actual simulation environment
        self.sim_trace = pyrtl.SimulationTrace()
        self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)
コード例 #16
0
ファイル: test_simulation.py プロジェクト: UCSBarchlab/PyRTL
    def test_minus_sim_overflow(self):
        pyrtl.reset_working_block()
        i = pyrtl.Input(8, 'i')
        o = pyrtl.Output(name='o')
        o <<= i - 1

        tracer = pyrtl.SimulationTrace()
        sim = self.sim(tracer=tracer)
        sim.step({i: 1})
        self.assertEqual(sim.inspect(o), 0)
        sim.step({i: 0})
        self.assertEqual(sim.inspect(o), 0x1ff)
コード例 #17
0
    def test_net_odd_wires(self):
        wire = pyrtl.WireVector(2, 'wire')
        net = self.new_net(args=(wire, wire))
        other_block = pyrtl.Block()
        wire._block = other_block
        self.invalid_net("net references different block", net)

        pyrtl.reset_working_block()
        wire = pyrtl.WireVector(2, 'wire')
        net = self.new_net(args=(wire,))
        pyrtl.working_block().remove_wirevector(wire)
        self.invalid_net("net with unknown source", net)
コード例 #18
0
ファイル: test_fastsimulation.py プロジェクト: LinChai/PyRTL
    def setUp(self):
        pyrtl.reset_working_block()
        bitwidth = 3
        self.a = pyrtl.Input(bitwidth=bitwidth)
        self.b = pyrtl.Input(bitwidth=bitwidth)
        self.sel = pyrtl.Input(bitwidth=1)
        self.muxout = pyrtl.Output(bitwidth=bitwidth, name='muxout')
        self.muxout <<= generate_full_mux(self.a, self.b, self.sel)

        # build the actual simulation environment
        self.sim_trace = pyrtl.SimulationTrace()
        self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)
コード例 #19
0
 def setUp(self):
     pyrtl.reset_working_block()
     self.bitwidth = 3
     self.addrwidth = 5
     self.output1 = pyrtl.Output(self.bitwidth, "output1")
     self.output2 = pyrtl.Output(self.bitwidth, "output2")
     self.mem_read_address1 = pyrtl.Input(self.addrwidth, name='mem_read_address1')
     self.mem_read_address2 = pyrtl.Input(self.addrwidth, name='mem_read_address2')
     self.mem_write_address = pyrtl.Input(self.addrwidth, name='mem_write_address')
     self.mem_write_data = pyrtl.Input(self.bitwidth, name='mem_write_data')
     self.memory = pyrtl.MemBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
                                  name='self.memory', max_read_ports=None)
コード例 #20
0
ファイル: test_libutils.py プロジェクト: DivyaJanaswamy/PyRTL
    def test_partition_sim(self):
        pyrtl.reset_working_block()
        wires, vals = utils.make_wires_and_values(exact_bitwidth=32, num_wires=1)
        out_wires = [pyrtl.Output(8, "o" + str(i)) for i in range(4)]
        partitioned_w = libutils.partition_wire(wires[0], 8)
        for p_wire, o_wire in zip(partitioned_w, out_wires):
            o_wire <<= p_wire

        out_vals = utils.sim_and_ret_outws(wires, vals)
        partitioned_vals = [[(val >> i) & 0xFF for i in (0, 8, 16, 24)] for val in vals[0]]
        true_vals = tuple(zip(*partitioned_vals))
        for index, wire in enumerate(out_wires):
            self.assertEqual(tuple(out_vals[wire]), true_vals[index])
コード例 #21
0
ファイル: test_simulation.py プロジェクト: UCSBarchlab/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     in1 = pyrtl.Input(4, "in1")
     in2 = pyrtl.Input(4, "in2")
     out1 = pyrtl.Output(4, "out1")
     out1 <<= (in1 ^ in2) + pyrtl.Const(1)
     out2 = pyrtl.Output(4, "out2")
     out2 <<= in1 | in2
     self.inputs = {
         'in1': [0, 1, 3, 15, 14],
         'in2':
         '66666',  # When a string, assumes each input is a single digit integer
     }
コード例 #22
0
    def test_partition_sim(self):
        pyrtl.reset_working_block()
        wires, vals = utils.make_inputs_and_values(exact_bitwidth=32, num_wires=1)
        out_wires = [pyrtl.Output(8, 'o' + str(i)) for i in range(4)]
        partitioned_w = libutils.partition_wire(wires[0], 8)
        for p_wire, o_wire in zip(partitioned_w, out_wires):
            o_wire <<= p_wire

        out_vals = utils.sim_and_ret_outws(wires, vals)
        partitioned_vals = [[(val >> i) & 0xff for i in (0, 8, 16, 24)] for val in vals[0]]
        true_vals = tuple(zip(*partitioned_vals))
        for index, wire in enumerate(out_wires):
            self.assertEqual(tuple(out_vals[wire.name]), true_vals[index])
コード例 #23
0
ファイル: test_passes.py プロジェクト: UCSBarchlab/PyRTL
    def test_order_dependent_ops(self):
        # subtract, lt, gt simarlarly are order dependent.
        # therefore we need to check that we aren't mangling them
        for op, opcode in ((operator.sub, '-'), (operator.gt, '>'), (operator.lt, '<')):
            pyrtl.reset_working_block()
            ins = [pyrtl.Input(5) for i in range(2)]
            outs = [pyrtl.Output(10) for i in range(2)]
            outs[0] <<= op(ins[1], ins[0])
            outs[1] <<= op(ins[0], ins[1])

            pyrtl.common_subexp_elimination()
            self.num_net_of_type(opcode, 2)
            self.num_net_of_type('w', 2)
            pyrtl.working_block().sanity_check()
コード例 #24
0
    def test_order_dependent_ops(self):
        # subtract, lt, gt simarlarly are order dependent.
        # therefore we need to check that we aren't mangling them
        for op, opcode in ((operator.sub, '-'), (operator.gt, '>'), (operator.lt, '<')):
            pyrtl.reset_working_block()
            ins = [pyrtl.Input(5) for i in range(2)]
            outs = [pyrtl.Output(10) for i in range(2)]
            outs[0] <<= op(ins[1], ins[0])
            outs[1] <<= op(ins[0], ins[1])

            pyrtl.common_subexp_elimination()
            self.num_net_of_type(opcode, 2)
            self.num_net_of_type('w', 2)
            pyrtl.working_block().sanity_check()
コード例 #25
0
def translate(args):
    if os.path.exists(args.v_dir):
        shutil.rmtree(args.v_dir)
    os.mkdir(args.v_dir)

    mod_name = args.module[0]
    py_mod_name = get_py_module_name(mod_name)
    exec('import {}'.format(py_mod_name))

    pyrtl.reset_working_block()

    exec('mod_inst = {}(depth_width=2)'.format(mod_name))

    with open(args.v_dir + '/' + mod_name + '.v', 'w+') as f:
        pyrtl.OutputToVerilog(f)
コード例 #26
0
ファイル: test_simulation.py プロジェクト: UCSBarchlab/PyRTL
    def test_step_multiple_nsteps_no_inputs(self):
        pyrtl.reset_working_block()
        a = pyrtl.Register(8)
        b = pyrtl.Output(8, 'b')
        a.next <<= a + 1
        b <<= a

        sim_trace = pyrtl.SimulationTrace()
        sim = self.sim(tracer=sim_trace)
        sim.step_multiple(nsteps=5)

        correct_output = ("--- Values in base 10 ---\n" "b 0 1 2 3 4\n")
        output = six.StringIO()
        sim_trace.print_trace(output)
        self.assertEqual(output.getvalue(), correct_output)
コード例 #27
0
ファイル: test_transform.py プロジェクト: UCSBarchlab/PyRTL
    def test_clone_wire_no_or_same_name_different_block(self):
        for clone_name in (None, 'a'):
            a = pyrtl.WireVector(1, 'a')
            b = pyrtl.Block()
            with pyrtl.set_working_block(b):
                w = pyrtl.clone_wire(a, name=clone_name)

            self.assertEqual(a.name, 'a')
            self.assertIs(pyrtl.working_block().wirevector_by_name['a'], a)
            self.assertEqual(pyrtl.working_block().wirevector_set, {a})

            self.assertEqual(w.name, 'a')
            self.assertIs(b.wirevector_by_name['a'], w)
            self.assertEqual(b.wirevector_set, {w})
            pyrtl.reset_working_block()
コード例 #28
0
    def setUp(self):
        pyrtl.reset_working_block()
        self.bitwidth = 68
        self.addrwidth = 32
        self.output1 = pyrtl.Output(self.bitwidth, "o1")
        self.output2 = pyrtl.Output(self.bitwidth, "o2")
        self.read_addr1 = pyrtl.Input(self.addrwidth)
        self.read_addr2 = pyrtl.Input(self.addrwidth)
        self.write_addr = pyrtl.Input(self.addrwidth)
        self.write_data = pyrtl.Input(self.bitwidth)
        self.mem = pyrtl.MemBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth, name='mem')
        self.output1 <<= self.mem[self.read_addr1]
        self.output2 <<= self.mem[self.read_addr2]
        self.mem[self.write_addr] <<= self.write_data

        # build the actual simulation environment
        self.sim_trace = pyrtl.SimulationTrace()
コード例 #29
0
ファイル: test_fastsimulation.py プロジェクト: LinChai/PyRTL
    def setUp(self):
        pyrtl.reset_working_block()
        self.bitwidth = 3
        self.addrwidth = 4
        self.output1 = pyrtl.Output(self.bitwidth, "o1")
        self.output2 = pyrtl.Output(self.bitwidth, "o2")
        self.read_addr1 = pyrtl.Input(self.addrwidth)
        self.read_addr2 = pyrtl.Input(self.addrwidth)
        self.write_addr = pyrtl.Input(self.addrwidth)
        self.write_data = pyrtl.Input(self.bitwidth)
        self.rom = pyrtl.MemBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
                                  name='rom')
        self.output1 <<= self.rom[self.read_addr1]
        self.output2 <<= self.rom[self.read_addr2]
        self.rom[self.write_addr] <<= self.write_data

        # build the actual simulation environment
        self.sim_trace = pyrtl.SimulationTrace()
コード例 #30
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 def wrapper(*args, **kwargs):
     assert len(args) == 0  # only keyword args allowed
     pyrtl.reset_working_block()
     # map inputs names
     race_kwargs = {k: r_from_str(k) for k, v in kwargs.items()}
     # build the test
     function(*args, **race_kwargs)
     # run the simulation
     o, t = sim_race(
         {race_kwargs[k]: v
          for k, v in kwargs.items() if k != 'output'})
     # check the result of the simulation is the same as the output argument
     sim_out = o['output']
     spec_out = kwargs['output']
     if sim_out != spec_out:
         raise RaceTestError('sim output "%s" != spec output "%s"' %
                             (sim_out, spec_out))
     pyrtl.reset_working_block()
     return t
コード例 #31
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def test_initial_empty():
    pyrtl.reset_working_block()
    model = fifo.FIFO(depth_width=4)
    tracer = pyrtl.SimulationTrace()
    sim = pyrtl.Simulation(tracer=tracer)
    sim.step({
        'wr_data_i': 0,
        'wr_en_i':   0,
        'rd_en_i':   0,
        'reset'  :   1,
        })
    sim.step({
        'wr_data_i': 0,
        'wr_en_i':   0,
        'rd_en_i':   0,
        'reset'  :   0,
        })

    assert tracer.trace['empty_o'][-1] == 1, 'FIFO should be empty after reset'
    assert tracer.trace['full_o'][-1]  == 0, 'FIFO should not be full after reset'
コード例 #32
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def evaluate_circuit(matrix, input_sequence, expected_output):
    """
    Given a matrix of `Gate`s, evaluate how well `expected_output` matches the
    actual output of the created circuit when given `input_sequence` as input.
    """
    # Initialize the circuit
    pyrtl.reset_working_block()

    # Create the initial 'connection points': inputs and registers
    circuit_inputs = [
        pyrtl.Input(1, str(inp)) for inp in range(len(input_sequence[0]))
    ]
    registers = mem_scan(matrix)
    connection_points = [*registers, *circuit_inputs]

    # Create the actual pyrtl circuit and link the outputs
    gate_matrix = translate_matrix_to_pyrtl(connection_points, matrix,
                                            len(registers))
    circuit_outputs = connect_outputs(gate_matrix, matrix)

    # Simulate and return correctness value between [0,1]
    output_bits = simulate_circuit(circuit_inputs, input_sequence,
                                   circuit_outputs)
    return calculate_correctness(expected_output, output_bits)
コード例 #33
0
ファイル: test_fastsimulation.py プロジェクト: LinChai/PyRTL
 def tearDown(self):
     pyrtl.reset_working_block()
コード例 #34
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ファイル: test_barrel.py プロジェクト: UCSBarchlab/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     self.inp_val = pyrtl.Input(8, 'inp_val')
     self.inp_shift = pyrtl.Input(2, 'inp_shift')
     self.out_zeros = pyrtl.Output(18, 'out_zeros')
     self.out_ones = pyrtl.Output(18, 'out_ones')
コード例 #35
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ファイル: test_core.py プロジェクト: UCSBarchlab/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     self.block_a = pyrtl.Block()
     self.block_b = pyrtl.Block()
コード例 #36
0
 def setUp(self):
     pyrtl.reset_working_block()
     self.bitwidth = 3
     self.r = pyrtl.Register(bitwidth=self.bitwidth)
     self.output = pyrtl.Output(bitwidth=self.bitwidth, name='r')
     self.output <<= self.r
コード例 #37
0
ファイル: test_simulation.py プロジェクト: UCSBarchlab/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     bitwidth = 3
     self.r = pyrtl.Register(bitwidth=bitwidth, name='r')
     self.result = _basic_add(self.r, pyrtl.Const(1).zero_extended(bitwidth))
     self.r.next <<= self.result
コード例 #38
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 def setUp(self):
     pyrtl.reset_working_block()
     self.aes = aes.AES()
     self.in_vector = pyrtl.Input(bitwidth=128, name='in_vector')
     self.out_vector = pyrtl.Output(bitwidth=128, name='out_vector')
コード例 #39
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ファイル: test_fastsimulation.py プロジェクト: LinChai/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     bitwidth = 3
     self.r = pyrtl.Register(bitwidth=bitwidth, name='r')
     self.sum, self.cout = generate_full_adder(self.r, pyrtl.Const(1).zero_extended(bitwidth))
     self.r.next <<= self.sum
コード例 #40
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ファイル: test_wire.py プロジェクト: DivyaJanaswamy/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     self.r = pyrtl.Register(bitwidth=3)
コード例 #41
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ファイル: test_helperfuncs.py プロジェクト: UCSBarchlab/PyRTL
 def test_wire_from_another_block(self):
     w = pyrtl.Input(1)
     pyrtl.reset_working_block()
     self.bad_rtl_assert(w, self.RTLSampleException())
コード例 #42
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ファイル: test_muxes.py プロジェクト: UCSBarchlab/PyRTL
 def setUpClass(cls):
     pyrtl.reset_working_block()
コード例 #43
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 def setUp(self):
     pyrtl.reset_working_block()
コード例 #44
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mem2_init = {addr: 9 for addr in range(8)}

# The simulation only recognizes initial values of memories when they are in a
# dictionary composing of memory : mem_values pairs.
memvals = {mem1: mem1_init, mem2: mem2_init}

# now run the simulation like before. Note the adding of the memory
# value map.
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace, memory_value_map=memvals)
for cycle in range(len(simvals['we'])):
    sim.step({k: int(v[cycle]) for k, v in simvals.items()})
sim_trace.render_trace()

# cleanup in preparation for the rom example
pyrtl.reset_working_block()

# --- Part 2: ROMs -----------------------------------------------------------

# ROMs are another type of memory. Unlike normal memories, ROMs are read only
# and therefore only have read ports. They are used to store predefined data

# There are two different ways to define the data stored in the ROMs
# either through passing a function or though a list or tuple


def rom_data_func(address):
    return 31 - 2 * address

rom_data_array = [rom_data_func(a) for a in range(16)]
コード例 #45
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 def setUp(self):
     pyrtl.reset_working_block()
     self.maxDiff = None
コード例 #46
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 def setUp(self):
     pyrtl.reset_working_block()
コード例 #47
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 def setUp(self):
     pyrtl.reset_working_block()
     self.in1, self.in2 = (pyrtl.Input(8, "in" + str(i)) for i in range(1, 3))
     self.out = pyrtl.Output(9, "out")
コード例 #48
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ファイル: test_libutils.py プロジェクト: UCSBarchlab/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     self.in1, self.in2 = (pyrtl.Input(8, "in"+str(i)) for i in range(1, 3))
     self.out = pyrtl.Output(9, "out")
コード例 #49
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 def setUp(self):
     pyrtl.reset_working_block()
     self.output = pyrtl.Output(name='r')
コード例 #50
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ファイル: test_inputoutput.py プロジェクト: UCSBarchlab/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     self.vnames = inputoutput._VerilogSanitizer("_sani_test")
コード例 #51
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ファイル: test_simulation.py プロジェクト: UCSBarchlab/PyRTL
 def setUp(self):
     pyrtl.reset_working_block()
     self.in1 = pyrtl.Input(8, "in1")
     self.in2 = pyrtl.Input(8, "in2")
     self.out = pyrtl.Output(16, "out")
コード例 #52
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 def tearDown(self):
     pyrtl.reset_working_block()
コード例 #53
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ファイル: example6-memory.py プロジェクト: jolting/PyRTL
mem2_init = {addr: 9 for addr in range(8)}

# The simulation only recognizes initial values of memories when they are in a
# dictionary composing of memory : mem_values pairs.
memvals = {mem1: mem1_init, mem2: mem2_init}

# now run the simulation like before. Note the adding of the memory
# value map.
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace, memory_value_map=memvals)
for cycle in range(len(simvals[we])):
    sim.step({k: int(v[cycle]) for k, v in simvals.items()})
sim_trace.render_trace()

# cleanup in preparation for the rom example
pyrtl.reset_working_block()

# --- Part 2: ROMs -----------------------------------------------------------

# ROMs are another type of memory. Unlike normal memories, ROMs are read only
# and therefore only have read ports. They are used to store predefined data

# There are two different ways to define the data stored in the ROMs
# either through passing a function or though a list or tuple


def rom_data_func(address):
    return 31 - 2 * address


rom_data_array = [rom_data_func(a) for a in range(16)]
コード例 #54
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 def setUp(self):
     pyrtl.reset_working_block()
     self.block = pyrtl.working_block()