def test_registers_written_ldr(self): # ldr r5, [pc, #44] arm1 = DARMInstruction(re("2c 50 9f e5"), 0, Instruction.HEX_STR) r1 = arm1.registers_written() self.assertTrue(AReg.R5 in r1) # ldr r6, [pc, #72] arm2 = DARMInstruction(re("48 60 9f e5"), 0, Instruction.HEX_STR) r2 = arm2.registers_written() self.assertTrue(AReg.R6 in r2)
def test_reg_read_write_pop_push(self): darm = DARMInstruction(re("f0 87 bd 08"), 0, Instruction.HEX_STR) self.assertEqual(2, len(darm.registers_read())) self.assertTrue(AReg.R13 in darm.registers_read()) self.assertTrue(AReg.CPSR in darm.registers_read()) self.assertEqual(8, len(darm.registers_written()))