if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':

panic("This script requires the MESI_CMP_directory protocol to be built.")

cpu_sequencers = []

#

# The ruby network creation expects the list of nodes in the system to be

# consistent with the NetDest list. Therefore the l1 controller nodes must be

# listed before the directory nodes and directory nodes before dma nodes, etc.

#

l1_cntrl_nodes = []

l2_cntrl_nodes = []

dir_cntrl_nodes = []

dma_cntrl_nodes = []

#

# Must create the individual controllers before the network to ensure the

# controller constructors are called before the network constructor

#

l2_bits = int(math.log(options.num_l2caches, 2))

block_size_bits = int(math.log(options.cacheline_size, 2))

cntrl_count = 0

for i in xrange(options.num_cpus):

#

# First create the Ruby objects associated with this cpu

#

l0i_cache = L1Cache(size = options.l0i_size,

assoc = options.l0i_assoc,

start_index_bit = block_size_bits,

is_icache = True)

l0d_cache = L1Cache(size = options.l0d_size,

assoc = options.l0d_assoc,

start_index_bit = block_size_bits,

is_icache = False)

l1_cache = L1Cache(size = options.l1_size,

assoc = options.l1_assoc,

start_index_bit = block_size_bits)

prefetcher = RubyPrefetcher.Prefetcher()

l1_cntrl = L1Cache_Controller(version = i,

cntrl_id = cntrl_count,

L0IcacheMemory = l0i_cache,

L0DcacheMemory = l0d_cache,

L1cacheMemory = l1_cache,

l2_select_num_bits = l2_bits,

send_evictions = (

options.cpu_type == "detailed"),

prefetcher = prefetcher,

ruby_system = ruby_system,

enable_prefetch = False)

cpu_seq = RubySequencer(version = i,

icache = l0i_cache,

dcache = l0d_cache,

ruby_system = ruby_system)

l1_cntrl.sequencer = cpu_seq

if piobus != None:

cpu_seq.pio_port = piobus.slave

exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)

#

# Add controllers and sequencers to the appropriate lists

#

cpu_sequencers.append(cpu_seq)

l1_cntrl_nodes.append(l1_cntrl)

cntrl_count += 1

l2_index_start = block_size_bits + l2_bits

for i in xrange(options.num_l2caches):

#

# First create the Ruby objects associated with this cpu

#

l2_cache = L2Cache(size = options.l2_size,

assoc = options.l2_assoc,

start_index_bit = l2_index_start)

l2_cntrl = L2Cache_Controller(version = i,

cntrl_id = cntrl_count,

L2cacheMemory = l2_cache,

ruby_system = ruby_system)

exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)

l2_cntrl_nodes.append(l2_cntrl)

cntrl_count += 1

phys_mem_size = sum(map(lambda mem: mem.range.size(),

system.memories.unproxy(system)))

mem_module_size = phys_mem_size / options.num_dirs

for i in xrange(options.num_dirs):

#

# Create the Ruby objects associated with the directory controller

#

mem_cntrl = RubyMemoryControl(version = i,

ruby_system = ruby_system)

dir_size = MemorySize('0B')

dir_size.value = mem_module_size

dir_cntrl = Directory_Controller(version = i,

cntrl_id = cntrl_count,

directory = \

RubyDirectoryMemory(version = i,

size = dir_size,

use_map =

options.use_map),

memBuffer = mem_cntrl,

ruby_system = ruby_system)

exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)

dir_cntrl_nodes.append(dir_cntrl)

cntrl_count += 1

for i, dma_port in enumerate(dma_ports):

#

# Create the Ruby objects associated with the dma controller

#

dma_seq = DMASequencer(version = i,

ruby_system = ruby_system)

dma_cntrl = DMA_Controller(version = i,

cntrl_id = cntrl_count,

dma_sequencer = dma_seq,

ruby_system = ruby_system)

exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)

exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)

dma_cntrl_nodes.append(dma_cntrl)

cntrl_count += 1

all_cntrls = l1_cntrl_nodes + \

l2_cntrl_nodes + \

dir_cntrl_nodes + \

dma_cntrl_nodes

topology = create_topology(all_cntrls, options)