This is a port of SystemVerilog (SV) Universal Verification Methodology (UVM) 1.2 to Python and cocotb. Only Icarus Verilog (iverilog) has been used for testing the code so far, but the plan is to include verilator in the regressions as well.

UVM is not currently supported by any open source/free tools. cocotb offers excellent solution to interact with any simulator (free/commercial), so testbenches can be written in Python as well. uvm-python tries to offer an API similar to the original SV version. This means that many UVM verificaton skills are transferable from SV to Python very easily.

The documentation is available on readthedocs.io in uvm-python HTML documentation.

You can install uvm-python as a normal Python package:

git clone https://github.com/tpoikela/uvm-python.git
cd uvm-python
python -m pip install --user .  # Omit --user for global installation

See Makefile for working examples. You can also use Makefiles in test/examples/simple as a template for your project.

See test/examples/simple/Makefile for working examples. More features/examples will be added incrementally.

To run all tests:

    SIM=icarus make test  # Use iverilog as a simulator

To run unit tests only:

    make test-unit  # Does not require simulator

uvm-python must be installed prior to running the example. You can find the source code for this example here. This example create a test component, register it with the UVM factory, and starts the test.

You can execute the example by running SIM=icarus make. Alternatively, you can run it with SIM=verilator make.

# File: Makefile
TOPLEVEL_LANG ?= verilog
VERILOG_SOURCES ?= new_dut.sv
TOPLEVEL := new_dut
MODULE   ?= new_test
include $(shell cocotb-config --makefiles)/Makefile.inc
include $(shell cocotb-config --makefiles)/Makefile.sim

The top-level module must match TOPLEVEL in Makefile:

// File: new_dut.sv
module new_dut(input clk, input rst, output[7:0] byte_out);
    assign byte_out = 8'hAB;
endmodule: new_dut

The Python test file name must match MODULE in Makefile:

# File: new_test.py
import cocotb
from cocotb.triggers import Timer
from uvm import *

class NewTest(UVMTest):
    @cocotb.coroutine
    def run_phase(self, phase):
        phase.raise_objection(self)
        yield Timer(100, "NS")
        phase.drop_objection(self)

uvm_component_utils(NewTest)

@cocotb.test()
def test_dut(dut):
    yield run_test('NewTest')

Current status: Testbenches can already be written with all the typical UVM components. UVM Phasing is in place, and working. Stimulus can be generated using hierarchical sequences. Register layer supports already read/write to registers (via frontdoor), and to memories (frontdoor and backdoor). TLM 1.0 is implemented, put/get/analysis interfaces are done, and master/slave interfaces work. Initial implementation of TLM2.0 has also been added. The table below summarizes the status:

NOTE: Despite the working state, the project is under development, and still missing a lot of functionality. Please try it out, and let me know if something you require should be added, or even better, add it yourself, test it and create a pull request!

Icarus Verilog (iverilog v11.0) and verilator (v4.020+) are free simulators, which can be used with cocotb. uvm-python uses cocotb to interface with these simulators.

Commercial simulators that work with cocotb can of course be used with uvm-python as well.