def decode_instruction(instr): op = substring(instr, 23, 20) instr_23_21 = substring(instr, 23, 21) if instr_23_21 == 0b000: # Multiply return MulA1 elif instr_23_21 == 0b001: # Multiply Accumulate return MlaA1 elif op == 0b0100: # Unsigned Multiply Accumulate Accumulate Long return UmaalA1 elif op == 0b0101: raise UndefinedInstructionException() elif op == 0b0110: # Multiply and Subtract return MlsA1 elif op == 0b0111: raise UndefinedInstructionException() elif instr_23_21 == 0b100: # Unsigned Multiply Long return UmullA1 elif instr_23_21 == 0b101: # Unsigned Multiply Accumulate Long return UmlalA1 elif instr_23_21 == 0b110: # Signed Multiply Long return SmullA1 elif instr_23_21 == 0b111: # Signed Multiply Accumulate Long return SmlalA1
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif (processor.registers.current_mode_is_user_or_system() or processor.registers.current_instr_set() == InstrSet.THUMB_EE): print('unpredictable') else: length = (4 * bit_count(self.registers, 1, 16)) + 4 address = processor.registers.get( self.n) if self.increment else sub( processor.registers.get(self.n), length, 32) if self.word_higher: address = add(address, 4, 32) for i in range(15): if bit_at(self.registers, i): processor.registers.set( i, processor.mem_a_get(address, 4)) address = add(address, 4, 32) new_pc_value = processor.mem_a_get(address, 4) if self.wback and not bit_at(self.registers, self.n): processor.registers.set( self.n, (add(processor.registers.get( self.n), length, 32) if self.increment else sub( processor.registers.get(self.n), length, 32))) if self.wback and bit_at(self.registers, self.n): processor.registers.set(self.n, 0x00000000) # unknown processor.registers.cpsr_write_by_instr( processor.registers.get_spsr(), 0b1111, True) if processor.registers.cpsr.m == 0b11010 and processor.registers.cpsr.j and processor.registers.cpsr.t: print('unpredictable') else: processor.branch_write_pc(new_pc_value)
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif (not processor.registers.current_mode_is_not_user() or processor.registers.current_instr_set() == InstrSet.THUMB_EE): print('unpredictable') else: address = (processor.registers.get(self.n) if self.increment else sub(processor.registers.get(self.n), 8, 32)) if self.word_higher: address = add(address, 4, 32) new_pc_value = processor.mem_a_get(address, 4) spsr_value = processor.mem_a_get(add(address, 4, 32), 4) if self.wback: processor.registers.set( self.n, (add(processor.registers.get(self.n), 8, 32) if self.increment else sub(processor.registers.get(self.n), 8, 32)) ) processor.registers.cpsr_write_by_instr(spsr_value, 0b1111, True) if (processor.registers.cpsr.m == 0b11010 and processor.registers.cpsr.j and processor.registers.cpsr.t): print('unpredictable') else: processor.branch_write_pc(new_pc_value)
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif processor.registers.current_mode_is_user_or_system(): print('unpredictable') elif self.mode == 0b11010: print('unpredictable') else: if not processor.registers.is_secure(): if self.mode == 0b10110 or (self.mode == 0b10001 and processor.registers.nsacr.rfr): print('unpredictable') base = processor.registers.get_rmode(13, self.mode) address = base if self.increment else sub(base, 8, 32) if self.word_higher: address = add(address, 0b100, 32) processor.mem_a_set(address, 4, processor.registers.get_lr()) processor.mem_a_set(add(address, 4, 32), 4, processor.registers.get_spsr()) if self.wback: processor.registers.set_rmode( 13, self.mode, add(base, 8, 32) if self.increment else sub( base, 8, 32))
def from_bitarray(instr, processor): coproc = substring(instr, 11, 8) rt = substring(instr, 15, 12) if substring(coproc, 3, 1) == 0b101: raise UndefinedInstructionException() else: return MrcMrc2A2(instr, cp=coproc, t=rt)
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif (not processor.registers.current_mode_is_not_user() or processor.registers.current_instr_set() == InstrSet.InstrSet_ThumbEE): print "unpredictable" else: address = (processor.registers.get(self.n) if self.increment else sub(processor.registers.get(self.n), BitArray(bin="1000"), 32)) if self.word_higher: address = add(address, BitArray(bin="100"), 32) new_pc_value = processor.mem_a_get(address, 4) spsr_value = processor.mem_a_get(add(address, BitArray(bin="100"), 32), 4) if self.wback: processor.registers.set( self.n, (add(processor.registers.get(self.n), BitArray(bin="1000"), 32) if self.increment else sub(processor.registers.get(self.n), BitArray(bin="1000"), 32)) ) processor.registers.cpsr_write_by_instr(spsr_value, BitArray(bin="1111"), True) if (processor.registers.cpsr.get_m() == "0b11010" and processor.registers.cpsr.get_j() and processor.registers.cpsr.get_t()): print "unpredictable" else: processor.branch_write_pc(new_pc_value)
def execute(self, processor): if self.is_enterx: if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() else: processor.registers.select_instr_set(InstrSet.THUMB_EE) else: processor.registers.select_instr_set(InstrSet.THUMB)
def decode_instruction(instr): instr_25_21 = substring(instr, 25, 21) instr_25_24 = substring(instr, 25, 24) instr_11_9 = substring(instr, 11, 9) instr_25 = bit_at(instr, 25) instr_20 = bit_at(instr, 20) instr_21 = bit_at(instr, 21) instr_24 = bit_at(instr, 24) instr_23 = bit_at(instr, 23) op = bit_at(instr, 4) op1 = substring(instr, 25, 20) rn = substring(instr, 19, 16) if instr_25_21 == 0b00000: raise UndefinedInstructionException() elif instr_25_24 == 0b11: # Supervisor Call return SvcA1 elif instr_11_9 != 0b101 and not instr_25 and not instr_20 and not ( not instr_24 and not instr_23 and not instr_21): # Store Coprocessor return StcStc2A1 elif instr_11_9 != 0b101 and not instr_25 and instr_20 and not ( not instr_24 and not instr_23 and not instr_21) and rn != 0b1111: # Load Coprocessor (immediate) return LdcLdc2ImmediateA1 elif instr_11_9 != 0b101 and not instr_25 and instr_20 and not ( not instr_24 and not instr_23 and not instr_21) and rn == 0b1111: # Load Coprocessor (literal) return LdcLdc2LiteralA1 elif instr_11_9 != 0b101 and op1 == 0b000100: # Move to Coprocessor from two ARM core registers return McrrMcrr2A1 elif instr_11_9 != 0b101 and op1 == 0b000101: # Move to two ARM core registers from Coprocessor return MrrcMrrc2A1 elif instr_11_9 != 0b101 and instr_25_24 == 0b10 and not op: # Coprocessor data operations return CdpCdp2A1 elif instr_11_9 != 0b101 and instr_25_24 == 0b10 and op and not instr_20: # Move to Coprocessor from ARM core register return McrMcr2A1 elif instr_11_9 != 0b101 and instr_25_24 == 0b10 and op and instr_20: # Move to ARM core register from Coprocessor return MrcMrc2A1 elif instr_11_9 != 0b101 and not instr_25 and not ( not instr_24 and not instr_23 and not instr_21): # Advanced SIMD, Floating-point raise NotImplementedError() elif instr_11_9 != 0b101 and instr_25_21 == 0b00010: # Advanced SIMD, Floating-point raise NotImplementedError() elif instr_11_9 != 0b101 and instr_25_24 == 0b10 and not op: # Floating-point data processing raise NotImplementedError() elif instr_11_9 != 0b101 and instr_25_24 == 0b10 and op: # Advanced SIMD, Floating-point raise NotImplementedError()
def from_bitarray(instr, processor): coproc = substring(instr, 11, 8) rt = substring(instr, 15, 12) if substring(coproc, 3, 1) == 0b101: raise UndefinedInstructionException() elif rt == 13: print('unpredictable') else: return MrcMrc2T2(instr, cp=coproc, t=rt)
def from_bitarray(instr, processor): n = 14 imm32 = substring(instr, 7, 0) if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif ((processor.in_it_block() and not processor.last_in_it_block()) or processor.registers.current_instr_set() == InstrSet.THUMB_EE): print('unpredictable') else: return SubsPcLrThumbT1(instr, imm32=imm32, n=n)
def from_bitarray(instr, processor): coproc = substring(instr, 11, 8) rt = substring(instr, 15, 12) rt2 = substring(instr, 19, 16) if substring(coproc, 3, 1) == 0b101: raise UndefinedInstructionException() elif rt == 15 or rt2 == 15 or (rt == 13 or rt2 == 13): print('unpredictable') else: return McrrMcrr2T2(instr, cp=coproc, t=rt, t2=rt2)
def execute(self, processor): if processor.condition_passed(): if have_security_ext( ) and processor.registers.current_mode_is_not_user(): if (have_virt_ext() and not processor.registers.is_secure() and not processor.registers.current_mode_is_hyp() and processor.registers.hcr.tsc): hsr_string = 0b0000000000000000000000000 processor.write_hsr(0b010011, hsr_string) processor.registers.take_hyp_trap_exception() else: if processor.registers.scr.scd: if processor.registers.is_secure(): print('unpredictable') else: raise UndefinedInstructionException() else: raise SMCException() else: raise UndefinedInstructionException()
def from_bitarray(instr, processor): imm32 = substring(instr, 7, 0) rt = substring(instr, 15, 12) rn = substring(instr, 19, 16) add = True post_index = False if rn == 0b1111: raise UndefinedInstructionException() elif rt in (13, 15): print('unpredictable') else: return StrtT1(instr, register_form=False, add=add, post_index=post_index, t=rt, n=rn, imm32=imm32)
def from_bitarray(instr, processor): imm8 = substring(instr, 7, 0) coproc = substring(instr, 11, 8) rn = substring(instr, 19, 16) wback = bit_at(instr, 21) add = bit_at(instr, 23) index = bit_at(instr, 24) imm32 = imm8 << 2 if substring(instr, 24, 21) == 0b0000: raise UndefinedInstructionException() else: return LdcLdc2ImmediateT1(instr, cp=coproc, n=rn, add=add, imm32=imm32, index=index, wback=wback)
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif processor.registers.current_mode_is_user_or_system(): print('unpredictable') else: operand2 = shift(processor.registers.get( self.m), 32, self.shift_t, self.shift_n, processor.registers.cpsr.c ) if self.register_form else self.imm32 if self.opcode == 0b0000: result = processor.registers.get(self.n) & operand2 elif self.opcode == 0b0001: result = processor.registers.get(self.n) ^ operand2 elif self.opcode == 0b0010: result = add_with_carry(processor.registers.get(self.n), bit_not(operand2, 32), 1)[0] elif self.opcode == 0b0011: result = add_with_carry( bit_not(processor.registers.get(self.n), 32), operand2, 1)[0] elif self.opcode == 0b0100: result = add_with_carry(processor.registers.get(self.n), operand2, 0)[0] elif self.opcode == 0b0101: result = add_with_carry(processor.registers.get(self.n), operand2, processor.registers.cpsr.c)[0] elif self.opcode == 0b0110: result = add_with_carry(processor.registers.get(self.n), bit_not(operand2, 32), processor.registers.cpsr.c)[0] elif self.opcode == 0b0111: result = add_with_carry( bit_not(processor.registers.get(self.n), 32), operand2, processor.registers.cpsr.c)[0] elif self.opcode == 0b1100: result = processor.registers.get(self.n) | operand2 elif self.opcode == 0b1101: result = operand2 elif self.opcode == 0b1110: result = processor.registers.get(self.n) & bit_not( operand2, 32) elif self.opcode == 0b1111: result = bit_not(operand2, 32) processor.registers.cpsr_write_by_instr( processor.registers.get_spsr(), 0b1111, True) if processor.registers.cpsr.m == 0b11010 and processor.registers.cpsr.j and processor.registers.cpsr.t: print('unpredictable') else: processor.branch_write_pc(result)
def from_bitarray(instr, processor): imm8 = substring(instr, 7, 0) coproc = substring(instr, 11, 8) index = bit_at(instr, 24) add = bit_at(instr, 23) wback = bit_at(instr, 21) if substring(coproc, 3, 1) == 0b101: raise UndefinedInstructionException() elif wback: print('unpredictable') else: imm32 = imm8 << 2 return LdcLdc2LiteralA2(instr, cp=coproc, add=add, imm32=imm32, index=index)
def from_bitarray(instr, processor): imm32 = substring(instr, 7, 0) wback = bit_at(instr, 8) add = bit_at(instr, 9) index = bit_at(instr, 10) rt = substring(instr, 15, 12) rn = substring(instr, 19, 16) if rn == 0b1111 or (not index and not wback): raise UndefinedInstructionException() elif rt in (13, 15) or (wback and rn == rt): print('unpredictable') else: return StrImmediateThumbT4(instr, add=add, wback=wback, index=index, t=rt, n=rn, imm32=imm32)
def from_bitarray(instr, processor): imm32 = substring(instr, 7, 0) rt = substring(instr, 15, 12) rn = substring(instr, 19, 16) index = bit_at(instr, 10) add = bit_at(instr, 9) wback = bit_at(instr, 8) if not index and not wback: raise UndefinedInstructionException() elif rt == 13 or (rt == 15 and wback) or (wback and rt == rn): print('unpredictable') else: return LdrshImmediateT2(instr, add=add, wback=wback, index=index, imm32=imm32, t=rt, n=rn)
def from_bitarray(instr, processor): imm32 = substring(instr, 7, 0) wback = bit_at(instr, 8) add = bit_at(instr, 9) index = bit_at(instr, 10) rt = substring(instr, 15, 12) rn = substring(instr, 19, 16) if not index and not wback: raise UndefinedInstructionException() elif (wback and rn == rt) or (rt == 15 and processor.in_it_block() and not processor.last_in_it_block()): print('unpredictable') else: return LdrImmediateThumbT4(instr, add=add, wback=wback, index=index, t=rt, n=rn, imm32=imm32)
def from_bitarray(instr, processor): imm8 = substring(instr, 7, 0) coproc = substring(instr, 11, 8) rn = substring(instr, 19, 16) wback = bit_at(instr, 21) add = bit_at(instr, 23) index = bit_at(instr, 24) imm32 = imm8 << 2 if substring(instr, 24, 21) == 0b0000: raise UndefinedInstructionException() elif rn == 15: print('unpredictable') else: return StcStc2T1(instr, cp=coproc, n=rn, add=add, imm32=imm32, index=index, wback=wback)
def from_bitarray(instr, processor): imm8 = substring(instr, 7, 0) coproc = substring(instr, 11, 8) w = bit_at(instr, 21) add = bit_at(instr, 23) index = bit_at(instr, 24) d = bit_at(instr, 22) if not index and not add and not d and not w: raise UndefinedInstructionException() elif w: print('unpredictable') else: imm32 = imm8 << 2 return LdcLdc2LiteralA1(instr, cp=coproc, add=add, imm32=imm32, index=index)
def from_bitarray(instr, processor): rm = substring(instr, 3, 0) imm2 = substring(instr, 5, 4) rt = substring(instr, 15, 12) rn = substring(instr, 19, 16) index = True add = True wback = False if rn == 0b1111: raise UndefinedInstructionException() elif rt in (13, 15) or rm in (13, 15): print('unpredictable') else: return StrhRegisterT2(instr, add=add, wback=wback, index=index, m=rm, t=rt, n=rn, shift_t=SRType.LSL, shift_n=imm2)
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif processor.registers.current_mode_is_user_or_system(): print "unpredictable" else: length = 4 * self.registers.count(1) address = processor.registers.get(self.n) if self.increment else sub( processor.registers.get(self.n), BitArray(uint=length, length=32), 32) if self.word_higher: address = add(address, BitArray(bin="100"), 32) for i in xrange(15): if self.registers[15 - i]: processor.registers.set_rmode(i, BitArray(bin="10000"), processor.mem_a_get(address, 4)) address = add(address, BitArray(bin="100"), 32)
def from_bitarray(instr, processor): imm8 = substring(instr, 7, 0) coproc = substring(instr, 11, 8) add = bit_at(instr, 23) index = bit_at(instr, 24) imm32 = imm8 << 2 if substring(instr, 23, 21) == 0b0000: raise UndefinedInstructionException() elif bit_at(instr, 21) or ( not index and processor.registers.current_instr_set() != InstrSet.ARM): print('unpredictable') else: return LdcLdc2LiteralT1(instr, cp=coproc, add=add, imm32=imm32, index=index)
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif processor.registers.current_mode_is_user_or_system(): print('unpredictable') else: length = 4 * bit_count(self.registers, 1, 16) address = processor.registers.get( self.n) if self.increment else sub( processor.registers.get(self.n), length, 32) if self.word_higher: address = add(address, 4, 32) for i in range(15): if bit_at(self.registers, i): processor.registers.set_rmode( i, 0b10000, processor.mem_a_get(address, 4)) address = add(address, 4, 32)
def from_bitarray(instr, processor): imm8 = substring(instr, 7, 0) coproc = substring(instr, 11, 8) rn = substring(instr, 19, 16) wback = bit_at(instr, 21) add = bit_at(instr, 23) index = bit_at(instr, 24) d = bit_at(instr, 22) if not index and not add and not d and not wback: raise UndefinedInstructionException() else: imm32 = imm8 << 2 return LdcLdc2ImmediateA1(instr, cp=coproc, n=rn, add=add, imm32=imm32, index=index, wback=wback)
def from_bitarray(instr, processor): imm32 = substring(instr, 11, 0) rt = substring(instr, 15, 12) rn = substring(instr, 19, 16) index = True add = True wback = False if rn == 0b1111: raise UndefinedInstructionException() elif rt in (13, 15): print('unpredictable') else: return StrhImmediateThumbT2(instr, add=add, wback=wback, index=index, t=rt, n=rn, imm32=imm32)
def from_bitarray(instr, processor): imm8 = substring(instr, 7, 0) coproc = substring(instr, 11, 8) rn = substring(instr, 19, 16) wback = bit_at(instr, 21) add = bit_at(instr, 23) index = bit_at(instr, 24) d = bit_at(instr, 22) if not index and not add and not d and not wback: raise UndefinedInstructionException() elif rn == 15 and wback: print('unpredictable') else: imm32 = imm8 << 2 return StcStc2A1(instr, cp=coproc, n=rn, add=add, imm32=imm32, index=index, wback=wback)
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif (processor.registers.current_mode_is_user_or_system() or processor.registers.current_instr_set() == InstrSet.InstrSet_ThumbEE): print "unpredictable" else: length = 4 * self.registers.count(1) + 4 address = processor.registers.get( self.n) if self.increment else sub( processor.registers.get(self.n), BitArray(uint=length, length=32), 32) if self.word_higher: address = add(address, BitArray(bin="100"), 32) for i in xrange(15): if self.registers[15 - i]: processor.registers.set( i, processor.mem_a_get(address, 4)) address = add(address, BitArray(bin="100"), 32) new_pc_value = processor.mem_a_get(address, 4) if self.wback and not self.registers[15 - self.n]: processor.registers.set( self.n, (add(processor.registers.get(self.n), BitArray(uint=length, length=32), 32) if self.increment else sub( processor.registers.get(self.n), BitArray(uint=length, length=32), 32))) if self.wback and self.registers[15 - self.n]: processor.registers.set(self.n, BitArray(length=32)) # unknown processor.registers.cpsr_write_by_instr( processor.registers.get_spsr(), BitArray(bin="1111"), True) if (processor.registers.cpsr.get_m() == "0b11010" and processor.registers.cpsr.get_j() and processor.registers.cpsr.get_t()): print "unpredictable" else: processor.branch_write_pc(new_pc_value)
def from_bitarray(instr, processor): rm = substring(instr, 3, 0) tbform = bit_at(instr, 5) t = bit_at(instr, 4) imm2 = substring(instr, 7, 6) rd = substring(instr, 11, 8) imm3 = substring(instr, 14, 12) rn = substring(instr, 19, 16) s = bit_at(instr, 20) shift_t, shift_n = decode_imm_shift(tbform << 1, chain(imm3, imm2, 2)) if s or t: raise UndefinedInstructionException() elif rn in (13, 15) or rm in (13, 15) or rd in (13, 15): print('unpredictable') else: return PkhT1(instr, tb_form=tbform, m=rm, d=rd, n=rn, shift_t=shift_t, shift_n=shift_n)