def remove_port_connection(source: Port, sink: Port): """! @brief Remove/Undo a connection between two Ports.""" source.outgoing.remove(sink) sink.incoming = None source.glue_signal = None sink.glue_signal = None sink.set_connected(False)
def assign_port_to_register( self, register_num: int, port: Port, to_bit_index: int ) -> bool: """! @brief Assign a Port as a part of a register as a data sink. @param register_num Define the number of the register to assign to @param port The Port to assign to the register @param to_bit_index The bit offset to assign to. register bit map: (31 downto 0) """ if to_bit_index > 31 or to_bit_index < 0: LOG.error("Index for register assignment is out of bounds!") raise ValueError(to_bit_index, "Out of bounds!", port) # If the register index does not have a register associated, add them while self.register_count <= register_num: if register_num == self.register_count: self.add_register(Register.status) else: # Empty registers for empty spots self.add_register(Register.none) # Update register type if necessary if self.register_config[register_num] == "AS_REG_NONE": self.modify_register_type(register_num, Register.status) elif self.register_config[register_num] == "AS_REG_CONTROL": self.modify_register_type(register_num, Register.both) # Get or create the register assignment signal try: reg_signal = self.reg_assign_map_status[register_num] except KeyError: reg_signal = self.define_signal( "s_register_id{}_status".format(register_num), data_type="std_logic_vector", data_width=Port.DataWidth(31, "downto", 0), ) self._assign_to_register(register_num, reg_signal) # Get or create the source signal if isinstance(port, GenericSignal): source = port else: self.__update_generics_list__() port.glue_signal = self.define_signal_based_on_port(port) self.chain.connect(port, port.glue_signal) source = port.glue_signal # Assign the source signal to the register assignment signal reg_signal.assign_to_this_vector(source, to_bit_index)