def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = False OPTS.spice_name = "" # Unset to use any simulator OPTS.analytical_delay = False # This is a hack to reload the characterizer __init__ with the spice version import characterizer reload(characterizer) from characterizer import delay if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name), -1) import sram debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") s = sram.sram(word_size=1, num_words=16, num_banks=1, name="sram_func_test") OPTS.check_lvsdrc = True tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) probe_address = "1" * s.addr_size probe_data = s.word_size - 1 debug.info( 1, "Probe address {0} probe data {1}".format(probe_address, probe_data)) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) d = delay.delay(s, tempspice, corner) d.set_probe(probe_address, probe_data) # This will exit if it doesn't find a feasible period import tech d.load = tech.spice["msflop_in_cap"] * 4 d.slew = tech.spice["rise_time"] * 2 feasible_period = d.find_feasible_period() os.remove(tempspice) OPTS.analytical_delay = True reload(characterizer) globals.end_openram()
def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) # we will manually run lvs/drc OPTS.check_lvsdrc = False OPTS.spice_name = "hspice" OPTS.analytical_delay = False import characterizer reload(characterizer) from characterizer import delay import sram debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") s = sram.sram(word_size=OPTS.config.word_size, num_words=OPTS.config.num_words, num_banks=OPTS.config.num_banks, name="sram_func_test") OPTS.check_lvsdrc = True tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) probe_address = "1" * s.addr_size probe_data = s.word_size - 1 debug.info( 1, "Probe address {0} probe data {1}".format(probe_address, probe_data)) d = delay.delay(s, tempspice) d.set_probe(probe_address, probe_data) # This will exit if it doesn't find a feasible period import tech load = tech.spice["FF_in_cap"] * 4 slew = tech.spice["rise_time"] * 2 feasible_period = d.find_feasible_period(load, slew) os.remove(tempspice) OPTS.analytical_delay = True reload(characterizer) globals.end_openram()
self.word_size = word_size self.num_words = num_words self.num_banks = num_banks c = reload(__import__(OPTS.bitcell)) self.mod_bitcell = getattr(c, OPTS.bitcell) self.bitcell = self.mod_bitcell() # to get the row, col, etc. self.compute_sizes() sram = fake_sram(OPTS.word_size, OPTS.num_words, OPTS.num_banks, OPTS.output_name) sp_file = OPTS.output_path+OPTS.output_name + ".sp" from characterizer import delay import tech # Set up the delay and set to the nominal corner d = delay.delay(sram, sp_file, ("TT", tech.spice["nom_supply_voltage"], tech.spice["nom_temperature"])) # Set the period d.period = period # Set the load of outputs and slew of inputs d.set_load_slew(load,slew) # Set the probe address/bit probe_address = "1" * sram.addr_size probe_data = sram.word_size - 1 d.set_probe(probe_address, probe_data) d.write_delay_stimulus() # Output info about this run report_status() print("Output files are:\n{0}stim.sp\n{0}sram.sp\n{0}reduced.sp".format(OPTS.output_path)) OPTS.openram_temp = old_openram_temp
def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = False OPTS.spice_name = "hspice" OPTS.analytical_delay = False # This is a hack to reload the characterizer __init__ with the spice version import characterizer reload(characterizer) from characterizer import delay if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name), -1) import sram debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") s = sram.sram(word_size=OPTS.word_size, num_words=OPTS.num_words, num_banks=OPTS.num_banks, name="sram1") OPTS.check_lvsdrc = True tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) probe_address = "1" * s.addr_size probe_data = s.word_size - 1 debug.info( 1, "Probe address {0} probe data {1}".format(probe_address, probe_data)) d = delay.delay(s, tempspice) import tech loads = [tech.spice["FF_in_cap"] * 4] slews = [tech.spice["rise_time"] * 2] data = d.analyze(probe_address, probe_data, slews, loads) #print data if OPTS.tech_name == "freepdk45": golden_data = { 'read1_power': 0.0345742, 'read0_power': 0.03526189999999999, 'write0_power': 0.0270014, 'delay1': [0.0573107], 'delay0': [0.07055809999999998], 'min_period': 0.234, 'write1_power': 0.0376625, 'slew0': [0.0284344], 'slew1': [0.0189185] } elif OPTS.tech_name == "scn3me_subm": golden_data = { 'read1_power': 11.2474, 'read0_power': 11.3148, 'write0_power': 6.9064, 'delay1': [1.0298], 'delay0': [1.4102], 'min_period': 4.063, 'write1_power': 11.6964, 'slew0': [1.3118], 'slew1': [0.9816656] } else: self.assertTrue(False) # other techs fail # Check if no too many or too few results self.assertTrue(len(data.keys()) == len(golden_data.keys())) # Check each result for k in data.keys(): if type(data[k]) == list: for i in range(len(data[k])): self.isclose(data[k][i], golden_data[k][i], 0.15) else: self.isclose(data[k], golden_data[k], 0.15) # reset these options OPTS.check_lvsdrc = True OPTS.analytical_delay = True reload(characterizer) globals.end_openram()
def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) # we will manually run lvs/drc OPTS.check_lvsdrc = False OPTS.spice_name = "ngspice" OPTS.analytical_delay = False # This is a hack to reload the characterizer __init__ with the spice version import characterizer reload(characterizer) from characterizer import delay import sram debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") s = sram.sram(word_size=OPTS.config.word_size, num_words=OPTS.config.num_words, num_banks=OPTS.config.num_banks, name="sram1") tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) probe_address = "1" * s.addr_size probe_data = s.word_size - 1 debug.info( 1, "Probe address {0} probe data {1}".format(probe_address, probe_data)) d = delay.delay(s, tempspice) import tech loads = [tech.spice["FF_in_cap"] * 4] slews = [tech.spice["rise_time"] * 2] data = d.analyze(probe_address, probe_data, slews, loads) if OPTS.tech_name == "freepdk45": golden_data = { 'read1_power': 0.026660760000000002, 'read0_power': 0.02711731, 'write0_power': 0.02501428, 'delay1': [0.04867702], 'delay0': [0.1423633], 'min_period': 0.332, 'write1_power': 0.024162890000000003, 'slew0': [0.02733451], 'slew1': [0.02121624] } elif OPTS.tech_name == "scn3me_subm": golden_data = { 'read1_power': 4.250786000000001, 'read0_power': 4.093461, 'write0_power': 2.762675, 'delay1': [0.920068], 'delay0': [2.051821], 'min_period': 6.563, 'write1_power': 2.4545719999999998, 'slew0': [1.342015], 'slew1': [1.040868] } else: self.assertTrue(False) # other techs fail # Check if no too many or too few results self.assertTrue(len(data.keys()) == len(golden_data.keys())) # Check each result for k in data.keys(): if type(data[k]) == list: for i in range(len(data[k])): self.assertTrue( isclose(data[k][i], golden_data[k][i], 0.15)) else: self.assertTrue(isclose(data[k], golden_data[k], 0.15)) # reset these options OPTS.check_lvsdrc = True OPTS.spice_name = "hspice" OPTS.analytical_delay = True reload(characterizer) globals.end_openram()
def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = False OPTS.spice_name = "ngspice" OPTS.analytical_delay = False # This is a hack to reload the characterizer __init__ with the spice version import characterizer reload(characterizer) from characterizer import delay if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name), -1) import sram import tech debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") s = sram.sram(word_size=OPTS.word_size, num_words=OPTS.num_words, num_banks=OPTS.num_banks, name="sram1") tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) probe_address = "1" * s.addr_size probe_data = s.word_size - 1 debug.info( 1, "Probe address {0} probe data {1}".format(probe_address, probe_data)) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) d = delay.delay(s, tempspice, corner) import tech loads = [tech.spice["msflop_in_cap"] * 4] slews = [tech.spice["rise_time"] * 2] data = d.analyze(probe_address, probe_data, slews, loads) #print data if OPTS.tech_name == "freepdk45": golden_data = { 'read1_power': 0.03308298, 'read0_power': 0.03866541, 'write0_power': 0.02695139, 'delay1': [0.05840294000000001], 'delay0': [0.40787249999999997], 'min_period': 0.781, 'write1_power': 0.037257830000000006, 'slew0': [0.035826199999999996], 'slew1': [0.02059459] } elif OPTS.tech_name == "scn3me_subm": golden_data = { 'read1_power': 11.416549999999999, 'read0_power': 11.44908, 'write0_power': 8.250219, 'delay1': [0.8018421], 'delay0': [1.085861], 'min_period': 2.734, 'write1_power': 11.718020000000001, 'slew0': [0.8273725], 'slew1': [0.5730144] } else: self.assertTrue(False) # other techs fail # Check if no too many or too few results self.assertTrue(len(data.keys()) == len(golden_data.keys())) # Check each result for k in data.keys(): if type(data[k]) == list: for i in range(len(data[k])): self.isclose(data[k][i], golden_data[k][i], 0.15) else: self.isclose(data[k], golden_data[k], 0.15) # reset these options OPTS.check_lvsdrc = True OPTS.spice_name = "hspice" OPTS.analytical_delay = True reload(characterizer) globals.end_openram()
def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = False OPTS.spice_name = "hspice" OPTS.analytical_delay = False # This is a hack to reload the characterizer __init__ with the spice version import characterizer reload(characterizer) from characterizer import delay if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name), -1) import sram import tech debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") s = sram.sram(word_size=OPTS.word_size, num_words=OPTS.num_words, num_banks=OPTS.num_banks, name="sram1") OPTS.check_lvsdrc = True tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) probe_address = "1" * s.addr_size probe_data = s.word_size - 1 debug.info( 1, "Probe address {0} probe data {1}".format(probe_address, probe_data)) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) d = delay.delay(s, tempspice, corner) import tech loads = [tech.spice["msflop_in_cap"] * 4] slews = [tech.spice["rise_time"] * 2] data = d.analyze(probe_address, probe_data, slews, loads) #print data if OPTS.tech_name == "freepdk45": golden_data = { 'leakage_power': 0.0006964536000000001, 'delay_lh': [0.0573055], 'read0_power': [0.0337812], 'read1_power': [0.032946500000000004], 'write1_power': [0.0361529], 'write0_power': [0.026179099999999997], 'slew_hl': [0.0285185], 'min_period': 0.205, 'delay_hl': [0.070554], 'slew_lh': [0.0190073] } elif OPTS.tech_name == "scn3me_subm": golden_data = { 'leakage_power': 0.0004004581, 'delay_lh': [0.6538954], 'read0_power': [9.7622], 'read1_power': [9.589], 'write1_power': [10.2578], 'write0_power': [6.928400000000001], 'slew_hl': [0.8321625], 'min_period': 2.344, 'delay_hl': [0.9019090999999999], 'slew_lh': [0.5896232] } else: self.assertTrue(False) # other techs fail # Check if no too many or too few results self.assertTrue(len(data.keys()) == len(golden_data.keys())) # Check each result for k in data.keys(): if type(data[k]) == list: for i in range(len(data[k])): self.isclose(data[k][i], golden_data[k][i], 0.15) else: self.isclose(data[k], golden_data[k], 0.15) # reset these options OPTS.check_lvsdrc = True OPTS.analytical_delay = True reload(characterizer) globals.end_openram()
def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) # we will manually run lvs/drc OPTS.check_lvsdrc = False OPTS.spice_name = "hspice" OPTS.analytical_delay = False # This is a hack to reload the characterizer __init__ with the spice version import characterizer reload(characterizer) from characterizer import delay import sram debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") s = sram.sram(word_size=OPTS.config.word_size, num_words=OPTS.config.num_words, num_banks=OPTS.config.num_banks, name="sram1") OPTS.check_lvsdrc = True tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) probe_address = "1" * s.addr_size probe_data = s.word_size - 1 debug.info( 1, "Probe address {0} probe data {1}".format(probe_address, probe_data)) d = delay.delay(s, tempspice) import tech loads = [tech.spice["FF_in_cap"] * 4] slews = [tech.spice["rise_time"] * 2] data = d.analyze(probe_address, probe_data, slews, loads) if OPTS.tech_name == "freepdk45": golden_data = { 'read1_power': 0.0296933, 'read0_power': 0.029897899999999998, 'write0_power': 0.0258029, 'delay1': [0.049100700000000004], 'delay0': [0.13766139999999996], 'min_period': 0.322, 'write1_power': 0.0260398, 'slew0': [0.0265264], 'slew1': [0.0195507] } elif OPTS.tech_name == "scn3me_subm": golden_data = { 'read1_power': 4.3678, 'read0_power': 4.3914, 'write0_power': 2.9394, 'delay1': [0.8901521], 'delay0': [2.001], 'min_period': 5.781, 'write1_power': 2.7163, 'slew0': [1.3044000000000002], 'slew1': [0.9904079] } else: self.assertTrue(False) # other techs fail # Check if no too many or too few results self.assertTrue(len(data.keys()) == len(golden_data.keys())) # Check each result for k in data.keys(): if type(data[k]) == list: for i in range(len(data[k])): self.assertTrue( isclose(data[k][i], golden_data[k][i], 0.15)) else: self.assertTrue(isclose(data[k], golden_data[k], 0.15)) # reset these options OPTS.check_lvsdrc = True OPTS.analytical_delay = True reload(characterizer) globals.end_openram()