def randomizeAll(self): u = self.u for intf in u._interfaces: if (intf not in (u.clk, u.rst_n, u.bus) and not isinstance(intf, BramPort_withoutClk)): self.randomize(intf) axi_randomize_per_channel(self, u.bus)
def test_read(self, N=10, randomize=False): u = self.u s_r = u.s_r axi = u.m m = AxiSimRam(axi=axi) M_DW = axi.DATA_WIDTH FRAME_WORD_CNT = ceil(u.S_ADDR_STEP / M_DW) r_data = [ i # self._rand.getrandbits(M_DW) for i in range(N * FRAME_WORD_CNT) ] # create data words for P4AppPort rd_data = self.pack_words(r_data, M_DW, s_r.DATA_WIDTH) for index, d in enumerate(r_data): index = (u.M_ADDR_OFFSET * 8 // M_DW) + index m.data[index] = d for addr, _ in enumerate(rd_data): s_r.addr._ag.data.append(addr) if randomize: axi_randomize_per_channel(self, axi) self.runSim(N * FRAME_WORD_CNT * 12 * CLK_PERIOD) readed = s_r.data._ag.data self.assertEqual(len(readed), len(rd_data)) for addr, (d_ref, d) in enumerate(zip(rd_data, readed)): self.assertValEqual(d, d_ref, addr)
def test_write(self, N=20, randomize=False): u = self.u s_w = u.s_w axi = u.m m = AxiSimRam(axi=axi) M_DW = axi.DATA_WIDTH FRAME_WORD_CNT = ceil((u.S_ADDR_STEP) / M_DW) w_data = [ i # self._rand.getrandbits(M_DW) for i in range(N * FRAME_WORD_CNT) ] # create data words for P4AppPort wr_data = self.pack_words(w_data, M_DW, s_w.DATA_WIDTH) for addr, frame in enumerate(wr_data): s_w._ag.data.append((addr, frame)) if randomize: axi_randomize_per_channel(self, axi) self.runSim(N * FRAME_WORD_CNT * 10 * CLK_PERIOD) w_m = mask( s_w.DATA_WIDTH) if s_w.DATA_WIDTH < axi.DATA_WIDTH else mask( axi.DATA_WIDTH) addr = u.M_ADDR_OFFSET inMem = m.getArray(addr, M_DW // 8, FRAME_WORD_CNT * N) inMem = [None if v is None else v & w_m for v in inMem] self.assertValSequenceEqual(inMem, w_data)
def _test_incr(self, indexes=[0, ], randomize=False): u = self.u u.dataIn._ag.data.extend(indexes) t = (20 + len(indexes) * 2) * CLK_PERIOD if randomize: axi_randomize_per_channel(self, u.m) self.randomize(u.dataIn) self.randomize(u.dataOut) t *= 5 self.runSim(t) # check if pipeline registers are empty for i in range(u.PIPELINE_CONFIG.WAIT_FOR_WRITE_ACK): valid = getattr(self.rtl_simulator.model.io, f"st{i:d}_valid") self.assertValEqual(valid.read(), 0, i) # check if main state fifo is empty ooo_fifo = self.rtl_simulator.model.ooo_fifo_inst.io self.assertValEqual(ooo_fifo.item_valid.read(), 0) self.assertValEqual(ooo_fifo.read_wait.read(), 1) # check if all transactions on AXI are finished self.assertEmpty(u.m.b._ag.data) self.assertEmpty(u.m.r._ag.data) # check output data itself ref_data = [(v, indexes[:i + 1].count(v)) for i, v in enumerate(indexes)] self.assertValSequenceEqual(u.dataOut._ag.data, ref_data) for i in sorted(set(indexes)): self.assertValEqual(self.m.data[i], indexes.count(i), i)
def randomize_all(self): axi_randomize_per_channel(self, self.u.s)
def randomize_all(self): for i in [self.u.m, self.u.s]: axi_randomize_per_channel(self, i)
def randomize_all(self): u = self.u for axi in [u.m, u.s]: axi_randomize_per_channel(self, axi)
def randomize_all(self): u = self.u axi_randomize_per_channel(self, u.s) axi_randomize_per_channel(self, u.m)
def randomize_all(self): self.randomize(self.u.w) axi_randomize_per_channel(self, self.u.m)
def _test_incr(self, inputs, randomize=False, mem_init={}): u = self.u ADDR_ITEM_STEP = 2**u.ADDR_OFFSET_W for i in range(2**u.ADDR_WIDTH // ADDR_ITEM_STEP): v = mem_init.get(i, 0) if v != 0: item_valid, key, value = v v = u.MAIN_STATE_T.from_py({ "item_valid": item_valid, "key": key, "value": value }) v = v._reinterpret_cast(u.m.w.data._dtype) self.m.data[i] = v u.dataIn._ag.data.extend(inputs) t = (40 + len(inputs) * 3) * CLK_PERIOD if randomize: axi_randomize_per_channel(self, u.m) self.randomize(u.dataIn) self.randomize(u.dataOut) t *= 5 self.runSim(t) # check if pipeline registers are empty for i in range(u.PIPELINE_CONFIG.WAIT_FOR_WRITE_ACK): valid = getattr(self.rtl_simulator.model.io, f"st{i:d}_valid") self.assertValEqual(valid.read(), 0, i) # check if main state fifo is empty ooo_fifo = self.rtl_simulator.model.ooo_fifo_inst.io self.assertValEqual(ooo_fifo.item_valid.read(), 0) self.assertValEqual(ooo_fifo.read_wait.read(), 1) # check if all transactions on AXI are finished self.assertEmpty(u.m.b._ag.data) self.assertEmpty(u.m.r._ag.data) # check output data itself dout = u.dataOut._ag.data mem = copy(mem_init) for _in, _out in zip(inputs, dout): (addr, (reset, (key_vld, key, data), _, operation)) = _in ( o_addr, (o_found_key_vld, o_found_key, o_found_data), (o_reset, (o_key_vld, o_key, o_data), o_match, o_operation), ) = _out # None or tuple(item_valid, key, data) cur = mem.get(addr, None) aeq = self.assertValEqual aeq(o_addr, addr) if operation == OP.LOOKUP: # lookup and increment if found if cur is not None and cur[0] and int(cur[1]) == key: # lookup sucess aeq(o_reset, 0) aeq(o_match, 1) aeq(o_found_key_vld, 1) aeq(o_found_key, key) aeq(o_found_data, cur[2] + 1) aeq(o_found_key_vld, 1) mem[addr] = (1, key, int(o_found_data)) else: # lookup fail aeq(o_reset, 0) aeq(o_match, 0) # key remained same aeq(o_key_vld, key_vld) aeq(o_key, key) aeq(o_data, data) # there was nothing so nothig should have been found aeq(o_found_key_vld, int(cur is not None and cur[0])) elif operation == OP.LOOKUP_OR_SWAP: # lookup and increment or swap if not found if cur is not None and cur[0] and int(cur[1]) == key: # lookup sucess aeq(o_reset, 0) aeq(o_match, 1) aeq(o_found_key_vld, 1) aeq(o_found_key, key) aeq(o_found_data, cur[2] + 1) aeq(o_found_key_vld, 1) mem[addr] = (1, key, int(o_found_data)) else: # swap raise NotImplementedError() elif operation == OP.SWAP: # swap no matter if the key was found or not, do not increment raise NotImplementedError() else: raise ValueError(operation) self.assertValEqual(o_operation, operation) self.assertEqual(len(dout), len(inputs)) # for i in sorted(set(inputs)): # self.assertValEqual(self.m.data[i], inputs.count(i), i) for i in range(2**u.ADDR_WIDTH // ADDR_ITEM_STEP): v = self.m.getStruct(i * ADDR_ITEM_STEP, u.MAIN_STATE_T) ref_v = mem.get(i, None) if ref_v is None or not ref_v[0]: aeq(v.item_valid, 0) else: aeq(v.item_valid, 1) aeq(v.key, ref_v[1]) aeq(v.value, ref_v[2])