def __init__(self, **kwargs): platform = sim.Platform() SoCSDRAM.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, ident="LiteX simulation example design", with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) if not self.integrated_main_ram_size: sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_refresh=False)) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
def __init__(self, platform, **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x10000) if kwargs.get('cpu_type', None) == 'mor1kx': dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) dict_set_max(kwargs, 'firmware_ram_size', 0x10000) if 'firmware_filename' not in kwargs: kwargs[ 'firmware_filename'] = "build/sim_{}_{}/software/firmware/firmware.fbi".format( self.__class__.__name__.lower()[:-3], kwargs.get('cpu_type', 'lm32')) clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM( firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.flash_boot_address = self.mem_map["firmware_ram"] define_flash_constants(self) # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings(memtype="SDR", dfi_databits=1 * 32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1)
def __init__(self, firmware_ram_size=0x10000, firmware_filename="firmware/firmware.bin", **kwargs): platform = sim.Platform() SoCSDRAM.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, integrated_sram_size=0x8000, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1) self.submodules.video_out = VideoOutCore(self.sdram.crossbar.get_port()) self.submodules.vga = VGAModel(platform.request("vga")) self.comb += self.video_out.source.connect(self.vga.sink)
def __init__(self, **kwargs): platform = versa_ecp5.Platform(toolchain="trellis") platform.add_extension(versa_ecp5._ecp5_soc_hat_io) sys_clk_freq = int(50e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, l2_size=32, integrated_rom_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = AS4C32M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_refresh=False)) # FIXME
def __init__(self, platform, **kwargs): clk_freq = 100*1000000 DbgSoC.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 6) sdram_module = MT41K128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(cmd_buffer_depth=8))
def __init__(self, **kwargs): platform = ulx3s.Platform(toolchain="trellis") sys_clk_freq = int(25e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, l2_size=32, integrated_rom_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = MT48LC16M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_refresh=False)) # FIXME
def __init__(self, platform): sys_clk_freq = int(75e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type="lm32", integrated_rom_size=0x8000) self.submodules.crg = _CRG(platform, sys_clk_freq) if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = M12L64322A(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_refresh=False)) # led blink led_counter = Signal(32) self.sync += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led").eq(led_counter[26])
def __init__(self, platform): sys_clk_freq = int(75e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type="picorv32", integrated_rom_size=0x6000, integrated_sram_size=8192) self.submodules.crg = crg = _CRG(platform, sys_clk_freq) self.submodules.bridge = UARTWishboneBridge(platform.request("dbgserial"), sys_clk_freq, baudrate=115200) self.add_wb_master(self.bridge.wishbone) self.submodules.heartbeat = Heartbeat(sys_clk_freq, 0.5, platform.request("user_led")) self.submodules.j600io = J600IO( platform.request("U600"), platform.request("U601"), platform.request("U604"), platform.request("U605"), None) self.add_wb_slave(mem_decoder(self.mem_map["j600io"]), self.j600io.bus) self.add_memory_region("j600io", self.mem_map["j600io"] | self.shadow_base, 0x10) self.submodules.ethphy = LiteEthPHYRGMII(platform.request("eth_clocks", 1), platform.request("eth", 1)) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(75e6)) platform.add_false_path_constraints(crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk) if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = M12L64322A(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_refresh=False))
def __init__(self, clocks, log_level, auto_precharge=False, with_refresh=True, trace_reset=0, disable_delay=False, masked_write=True, double_rate_phy=False, finish_after_memtest=False, **kwargs): platform = Platform() sys_clk_freq = clocks["sys"]["freq_hz"] # SoCCore ---------------------------------------------------------------------------------- super().__init__(platform, clk_freq=sys_clk_freq, ident="LiteX Simulation", ident_version=True, cpu_variant="minimal", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, clocks.names()) # Debugging -------------------------------------------------------------------------------- platform.add_debug(self, reset=trace_reset) # LPDDR4 ----------------------------------------------------------------------------------- sdram_module = litedram_modules.MT53E256M16D1(sys_clk_freq, "1:8") pads = platform.request("lpddr4") sim_phy_cls = DoubleRateLPDDR4SimPHY if double_rate_phy else LPDDR4SimPHY self.submodules.ddrphy = sim_phy_cls( sys_clk_freq=sys_clk_freq, aligned_reset_zero=True, masked_write=masked_write, ) # fake delays (make no nsense in simulation, but sdram.c expects them) self.ddrphy._rdly_dq_rst = CSR() self.ddrphy._rdly_dq_inc = CSR() self.add_csr("ddrphy") for p in [ "clk_p", "clk_n", "cke", "odt", "reset_n", "cs", "ca", "dq", "dqs", "dmi" ]: self.comb += getattr(pads, p).eq(getattr(self.ddrphy.pads, p)) controller_settings = ControllerSettings() controller_settings.auto_precharge = auto_precharge controller_settings.with_refresh = with_refresh self.add_sdram("sdram", phy=self.ddrphy, module=sdram_module, origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=False, controller_settings=controller_settings) # Reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024) self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024) # LPDDR4 Sim ------------------------------------------------------------------------------- self.submodules.lpddr4sim = LPDDR4Sim( pads=self.ddrphy.pads, cl=self.sdram.controller.settings.phy.cl, cwl=self.sdram.controller.settings.phy.cwl, sys_clk_freq=sys_clk_freq, log_level=log_level, disable_delay=disable_delay, ) self.add_csr("lpddr4sim") self.add_constant("CONFIG_SIM_DISABLE_BIOS_PROMPT") if disable_delay: self.add_constant("CONFIG_DISABLE_DELAYS") if finish_after_memtest: self.submodules.ddrctrl = LiteDRAMCoreControl() self.add_csr("ddrctrl") self.sync += If(self.ddrctrl.init_done.storage, Finish()) # Reuse DFITimingsChecker from phy/model.py nphases = self.sdram.controller.settings.phy.nphases timings = {"tCK": (1e9 / sys_clk_freq) / nphases} for name in _speedgrade_timings + _technology_timings: timings[name] = sdram_module.get(name) self.submodules.dfi_timings_checker = DFITimingsChecker( dfi=self.ddrphy.dfi, nbanks=2**self.sdram.controller.settings.geom.bankbits, nphases=nphases, timings=timings, refresh_mode=sdram_module.timing_settings.fine_refresh_mode, memtype=self.sdram.controller.settings.phy.memtype, verbose=False, ) # Debug info ------------------------------------------------------------------------------- def dump(obj): print() print(" " + obj.__class__.__name__) print(" " + "-" * len(obj.__class__.__name__)) d = obj if isinstance(obj, dict) else vars(obj) for var, val in d.items(): if var == "self": continue if isinstance(val, Signal): val = "Signal(reset={})".format(val.reset.value) print(" {}: {}".format(var, val)) print("=" * 80) dump(clocks) dump(self.ddrphy.settings) dump(sdram_module.geom_settings) dump(sdram_module.timing_settings) print() print("=" * 80)
def __init__(self, platform, core_config, **kwargs): platform.add_extension(get_common_ios()) # Parameters ------------------------------------------------------------------------------- sys_clk_freq = core_config["sys_clk_freq"] cpu_type = core_config["cpu"] cpu_variant = core_config.get("cpu_variant", "standard") csr_alignment = core_config.get("csr_alignment", 32) csr_data_width = core_config.get("csr_data_width", 8) if cpu_type is None: kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 0 kwargs["with_uart"] = False kwargs["with_timer"] = False kwargs["with_ctrl"] = False # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, cpu_type=cpu_type, cpu_variant=cpu_variant, csr_data_width=csr_data_width, csr_alignment=csr_alignment, **kwargs) # CRG -------------------------------------------------------------------------------------- if isinstance(platform, SimPlatform): self.submodules.crg = CRG(platform.request("clk")) elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: self.submodules.crg = crg = LiteDRAMECP5DDRPHYCRG( platform, core_config) elif core_config["sdram_phy"] in [ litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY ]: self.submodules.crg = LiteDRAMS7DDRPHYCRG(platform, core_config) # DRAM ------------------------------------------------------------------------------------- platform.add_extension(get_dram_ios(core_config)) sdram_module = core_config["sdram_module"]( sys_clk_freq, "1:4" if core_config["memtype"] == "DDR3" else "1:2") # Sim if isinstance(platform, SimPlatform): from litex.tools.litex_sim import get_sdram_phy_settings sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings phy_settings = get_sdram_phy_settings( memtype=sdram_module.memtype, data_width=core_config["sdram_module_nb"] * 8, clk_freq=sdram_clk_freq) self.submodules.ddrphy = SDRAMPHYModel(module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq) # ECP5DDRPHY elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: assert core_config["memtype"] in ["DDR3"] self.submodules.ddrphy = core_config["sdram_phy"]( pads=platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.comb += crg.stop.eq(self.ddrphy.init.stop) self.add_constant("ECP5DDRPHY") sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2") # S7DDRPHY elif core_config["sdram_phy"] in [ litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY ]: assert core_config["memtype"] in ["DDR2", "DDR3"] self.submodules.ddrphy = core_config["sdram_phy"]( pads=platform.request("ddram"), memtype=core_config["memtype"], nphases=4 if core_config["memtype"] == "DDR3" else 2, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=core_config["iodelay_clk_freq"], cmd_latency=core_config["cmd_latency"]) self.add_constant("CMD_DELAY", core_config["cmd_delay"]) if core_config["memtype"] == "DDR3": self.ddrphy.settings.add_electrical_settings( rtt_nom=core_config["rtt_nom"], rtt_wr=core_config["rtt_wr"], ron=core_config["ron"]) self.add_csr("ddrphy") controller_settings = controller_settings = ControllerSettings( cmd_buffer_depth=core_config["cmd_buffer_depth"]) self.add_sdram( "sdram", phy=self.ddrphy, module=sdram_module, origin=self.mem_map["main_ram"], size= 0x01000000, # Only expose 16MB to the CPU, enough for Init/Calib. with_soc_interconnect=cpu_type is not None, l2_cache_size=8, l2_cache_min_data_width=0, controller_settings=controller_settings, ) # DRAM Control/Status ---------------------------------------------------------------------- # Expose calibration status to user. self.submodules.ddrctrl = LiteDRAMCoreControl() self.add_csr("ddrctrl") self.comb += platform.request("init_done").eq( self.ddrctrl.init_done.storage) self.comb += platform.request("init_error").eq( self.ddrctrl.init_error.storage) # If no CPU, expose a bus control interface to user. if cpu_type is None: wb_bus = wishbone.Interface() self.bus.add_master(master=wb_bus) platform.add_extension(wb_bus.get_ios("wb_ctrl")) wb_pads = platform.request("wb_ctrl") self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave") # User ports ------------------------------------------------------------------------------- self.comb += [ platform.request("user_clk").eq(ClockSignal()), platform.request("user_rst").eq(ResetSignal()) ] for name, port in core_config["user_ports"].items(): # Native ------------------------------------------------------------------------------- if port["type"] == "native": user_port = self.sdram.crossbar.get_port() platform.add_extension( get_native_user_port_ios(name, user_port.address_width, user_port.data_width)) _user_port_io = platform.request("user_port_{}".format(name)) self.comb += [ # cmd user_port.cmd.valid.eq(_user_port_io.cmd_valid), _user_port_io.cmd_ready.eq(user_port.cmd.ready), user_port.cmd.we.eq(_user_port_io.cmd_we), user_port.cmd.addr.eq(_user_port_io.cmd_addr), # wdata user_port.wdata.valid.eq(_user_port_io.wdata_valid), _user_port_io.wdata_ready.eq(user_port.wdata.ready), user_port.wdata.we.eq(_user_port_io.wdata_we), user_port.wdata.data.eq(_user_port_io.wdata_data), # rdata _user_port_io.rdata_valid.eq(user_port.rdata.valid), user_port.rdata.ready.eq(_user_port_io.rdata_ready), _user_port_io.rdata_data.eq(user_port.rdata.data), ] # Wishbone ----------------------------------------------------------------------------- elif port["type"] == "wishbone": user_port = self.sdram.crossbar.get_port() wb_port = wishbone.Interface(user_port.data_width, user_port.address_width) wishbone2native = LiteDRAMWishbone2Native(wb_port, user_port) self.submodules += wishbone2native platform.add_extension( get_wishbone_user_port_ios(name, len(wb_port.adr), len(wb_port.dat_w))) _wb_port_io = platform.request("user_port_{}".format(name)) self.comb += [ wb_port.adr.eq(_wb_port_io.adr), wb_port.dat_w.eq(_wb_port_io.dat_w), _wb_port_io.dat_r.eq(wb_port.dat_r), wb_port.sel.eq(_wb_port_io.sel), wb_port.cyc.eq(_wb_port_io.cyc), wb_port.stb.eq(_wb_port_io.stb), _wb_port_io.ack.eq(wb_port.ack), wb_port.we.eq(_wb_port_io.we), _wb_port_io.err.eq(wb_port.err), ] # AXI ---------------------------------------------------------------------------------- elif port["type"] == "axi": user_port = self.sdram.crossbar.get_port() axi_port = LiteDRAMAXIPort( user_port.data_width, user_port.address_width + log2_int(user_port.data_width // 8), port["id_width"]) axi2native = LiteDRAMAXI2Native(axi_port, user_port) self.submodules += axi2native platform.add_extension( get_axi_user_port_ios(name, axi_port.address_width, axi_port.data_width, port["id_width"])) _axi_port_io = platform.request("user_port_{}".format(name)) self.comb += [ # aw axi_port.aw.valid.eq(_axi_port_io.awvalid), _axi_port_io.awready.eq(axi_port.aw.ready), axi_port.aw.addr.eq(_axi_port_io.awaddr), axi_port.aw.burst.eq(_axi_port_io.awburst), axi_port.aw.len.eq(_axi_port_io.awlen), axi_port.aw.size.eq(_axi_port_io.awsize), axi_port.aw.id.eq(_axi_port_io.awid), # w axi_port.w.valid.eq(_axi_port_io.wvalid), _axi_port_io.wready.eq(axi_port.w.ready), axi_port.w.last.eq(_axi_port_io.wlast), axi_port.w.strb.eq(_axi_port_io.wstrb), axi_port.w.data.eq(_axi_port_io.wdata), # b _axi_port_io.bvalid.eq(axi_port.b.valid), axi_port.b.ready.eq(_axi_port_io.bready), _axi_port_io.bresp.eq(axi_port.b.resp), _axi_port_io.bid.eq(axi_port.b.id), # ar axi_port.ar.valid.eq(_axi_port_io.arvalid), _axi_port_io.arready.eq(axi_port.ar.ready), axi_port.ar.addr.eq(_axi_port_io.araddr), axi_port.ar.burst.eq(_axi_port_io.arburst), axi_port.ar.len.eq(_axi_port_io.arlen), axi_port.ar.size.eq(_axi_port_io.arsize), axi_port.ar.id.eq(_axi_port_io.arid), # r _axi_port_io.rvalid.eq(axi_port.r.valid), axi_port.r.ready.eq(_axi_port_io.rready), _axi_port_io.rlast.eq(axi_port.r.last), _axi_port_io.rresp.eq(axi_port.r.resp), _axi_port_io.rdata.eq(axi_port.r.data), _axi_port_io.rid.eq(axi_port.r.id), ] # FIFO --------------------------------------------------------------------------------- elif port["type"] == "fifo": platform.add_extension( get_fifo_user_port_ios(name, user_port.data_width)) _user_fifo_io = platform.request("user_fifo_{}".format(name)) fifo = LiteDRAMFIFO( data_width=user_port.data_width, base=port["base"], depth=port["depth"], write_port=self.sdram.crossbar.get_port("write"), write_threshold=port["depth"] - 32, # FIXME read_port=self.sdram.crossbar.get_port("read"), read_threshold=32 # FIXME ) self.submodules += fifo self.comb += [ # in fifo.sink.valid.eq(_user_fifo_io.in_valid), _user_fifo_io.in_ready.eq(fifo.sink.ready), fifo.sink.data.eq(_user_fifo_io.in_data), # out _user_fifo_io.out_valid.eq(fifo.source.valid), fifo.source.ready.eq(_user_fifo_io.out_ready), _user_fifo_io.out_data.eq(fifo.source.data), ] else: raise ValueError("Unsupported port type: {}".format( port["type"]))
def __init__(self, *, args, sys_clk_freq, sdram_module_cls, sdram_module_speedgrade=None, sdram_module_spd_file=None, ip_address="192.168.100.50", mac_address=0x10e2d5000001, udp_port=1234, **kwargs): self.args = args self.sys_clk_freq = sys_clk_freq self.ip_address = ip_address self.mac_address = mac_address self.udp_port = udp_port # Platform --------------------------------------------------------------------------------- if not args.sim: self.platform = self.get_platform() else: self.platform = SimPlatform() githash = git.Repo( '.', search_parent_directories=True).git.rev_parse("HEAD") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__( self, self.platform, sys_clk_freq, ident="LiteX Row Hammer Tester SoC on {}, git: {}".format( self.platform.device, githash), ident_version=True, integrated_rom_mode='rw' if args.rw_bios_mem else 'r', **kwargs) # CRG -------------------------------------------------------------------------------------- if not args.sim: self.submodules.crg = self.get_crg() else: self.submodules.crg = CRG(self.platform.request('sys_clk')) # Add dynamic simulation trace control, start enabled self.platform.add_debug(self, reset=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=self.platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds") # SDRAM PHY -------------------------------------------------------------------------------- if sdram_module_spd_file is not None: self.logger.info('Using DRAM module {} data: {}'.format( colorer('SPD'), sdram_module_spd_file)) with open(sdram_module_spd_file, 'rb') as f: spd_data = f.read() module = SDRAMModule.from_spd_data(spd_data, self.sys_clk_freq) else: ratio = self.get_sdram_ratio() self.logger.info('Using DRAM module {} ratio {}'.format( colorer(sdram_module_cls.__name__), colorer(ratio))) module = sdram_module_cls(self.sys_clk_freq, ratio, speedgrade=sdram_module_speedgrade) if args.sim: # Use the hardware platform to retrieve values for simulation hw_pads = self.get_platform().request('ddram') core_config = dict( sdram_module_nb=len(hw_pads.dq) // 8, # number of byte groups sdram_rank_nb=len(hw_pads.cs_n), # number of ranks sdram_module=module, memtype=module.memtype, ) # Add IO pins self.platform.add_extension(get_dram_ios(core_config)) phy_settings = get_sdram_phy_settings( memtype=module.memtype, data_width=core_config["sdram_module_nb"] * 8, clk_freq=sys_clk_freq) self.submodules.ddrphy = SDRAMPHYModel( module=module, settings=phy_settings, clk_freq=sys_clk_freq, verbosity=3, ) else: # hardware self.submodules.ddrphy = self.get_ddrphy() self.add_csr("ddrphy") # SDRAM Controller-------------------------------------------------------------------------- class ControllerDynamicSettings(Module, AutoCSR, AutoDoc, ModuleDoc): """Allows to change LiteDRAMController behaviour at runtime""" def __init__(self): self.refresh = CSRStorage( reset=1, description="Enable/disable Refresh commands sending") self.submodules.controller_settings = ControllerDynamicSettings() self.add_csr("controller_settings") controller_settings = ControllerSettings() controller_settings.with_auto_precharge = True controller_settings.with_refresh = self.controller_settings.refresh.storage controller_settings.refresh_cls = SyncableRefresher assert self.ddrphy.settings.memtype == module.memtype, \ 'Wrong DRAM module type: {} vs {}'.format(self.ddrphy.settings.memtype, module.memtype) self.add_sdram("sdram", phy=self.ddrphy, module=module, origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=0, controller_settings=controller_settings) # CPU will report that leveling finished by writing to ddrctrl CSRs self.submodules.ddrctrl = LiteDRAMCoreControl() self.add_csr("ddrctrl") # Ethernet / Etherbone --------------------------------------------------------------------- if not args.sim: self.add_host_bridge() else: # simulation self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth")) self.add_csr("ethphy") # Ethernet Core ethcore = LiteEthUDPIPCore(self.ethphy, ip_address=self.ip_address, mac_address=self.mac_address, clk_freq=self.sys_clk_freq) self.submodules.ethcore = ethcore # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, self.udp_port, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Rowhammer -------------------------------------------------------------------------------- self.submodules.rowhammer_dma = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma) self.add_csr("rowhammer") # Bist ------------------------------------------------------------------------------------- if not args.no_memory_bist: pattern_data_size = int(args.pattern_data_size, 0) phy_settings = self.sdram.controller.settings.phy pattern_data_width = phy_settings.dfi_databits * phy_settings.nphases pattern_length = pattern_data_size // (pattern_data_width // 8) assert pattern_data_size % (pattern_data_width//8) == 0, \ 'Pattern data memory size must be multiple of {} bytes'.format(pattern_data_width//8) self.submodules.pattern_mem = PatternMemory( data_width=pattern_data_width, mem_depth=pattern_length) self.add_memory(self.pattern_mem.data, name='pattern_data', origin=0x20000000) self.add_memory(self.pattern_mem.addr, name='pattern_addr', origin=0x21000000) self.logger.info( '{}: Length: {}, Data Width: {}-bit, Address width: {}-bit'. format(colorer('BIST pattern'), colorer(pattern_length), colorer(pattern_data_width), colorer(32))) assert controller_settings.address_mapping == 'ROW_BANK_COL' row_offset = controller_settings.geom.bankbits + controller_settings.geom.colbits inversion_kwargs = dict( rowbits=int(self.args.bist_inversion_rowbits, 0), row_shift=row_offset - self.sdram.controller.interface.address_align, ) # Writer dram_wr_port = self.sdram.crossbar.get_port() self.submodules.writer = Writer(dram_wr_port, self.pattern_mem, **inversion_kwargs) self.writer.add_csrs() self.add_csr('writer') # Reader dram_rd_port = self.sdram.crossbar.get_port() self.submodules.reader = Reader(dram_rd_port, self.pattern_mem, **inversion_kwargs) self.reader.add_csrs() self.add_csr('reader') assert pattern_data_width == dram_wr_port.data_width assert pattern_data_width == dram_rd_port.data_width # Payload executor ------------------------------------------------------------------------- if not args.no_payload_executor: # TODO: disconnect bus during payload execution phy_settings = self.sdram.controller.settings.phy scratchpad_width = phy_settings.dfi_databits * phy_settings.nphases payload_size = int(args.payload_size, 0) scratchpad_size = int(args.scratchpad_size, 0) assert payload_size % 4 == 0, 'Payload memory size must be multiple of 4 bytes' assert scratchpad_size % (scratchpad_width//8) == 0, \ 'Scratchpad memory size must be multiple of {} bytes'.format(scratchpad_width//8) scratchpad_depth = scratchpad_size // (scratchpad_width // 8) payload_mem = Memory(32, payload_size // 4) scratchpad_mem = Memory(scratchpad_width, scratchpad_depth) self.specials += payload_mem, scratchpad_mem self.add_memory(payload_mem, name='payload', origin=0x30000000) self.add_memory(scratchpad_mem, name='scratchpad', origin=0x31000000, mode='r') self.logger.info('{}: Length: {}, Data Width: {}-bit'.format( colorer('Instruction payload'), colorer(payload_size // 4), colorer(32))) self.logger.info('{}: Length: {}, Data Width: {}-bit'.format( colorer('Scratchpad memory'), colorer(scratchpad_depth), colorer(scratchpad_width))) self.submodules.dfi_switch = DFISwitch( with_refresh=self.sdram.controller.settings.with_refresh, dfii=self.sdram.dfii, refresher_reset=self.sdram.controller.refresher.reset, ) self.dfi_switch.add_csrs() self.add_csr('dfi_switch') self.submodules.payload_executor = PayloadExecutor( mem_payload=payload_mem, mem_scratchpad=scratchpad_mem, dfi_switch=self.dfi_switch, nranks=self.sdram.controller.settings.phy.nranks, bankbits=self.sdram.controller.settings.geom.bankbits, rowbits=self.sdram.controller.settings.geom.rowbits, colbits=self.sdram.controller.settings.geom.colbits, rdphase=self.sdram.controller.settings.phy.rdphase, ) self.payload_executor.add_csrs() self.add_csr('payload_executor')
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), args=None, ip_address="192.168.100.50", mac_address=0x10e2d5000001, udp_port=1234, **kwargs): if not args.sim: platform = arty.Platform(toolchain=toolchain) else: platform = Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- if not args.sim: self.submodules.crg = _CRG(platform, sys_clk_freq, args) else: self.submodules.crg = CRG(platform.request("sys_clk")) # DDR3 SDRAM ------------------------------------------------------------------------------- if not args.sim: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) else: from litedram.gen import get_dram_ios core_config = dict() core_config["sdram_module_nb"] = 2 # Number of byte groups core_config["sdram_rank_nb"] = 1 # Number of ranks core_config['sdram_module'] = getattr(litedram_modules, 'MT41K128M16') core_config["memtype"] = "DDR3" # DRAM type platform.add_extension(get_dram_ios(core_config)) sdram_module = core_config["sdram_module"]( sys_clk_freq, rate={ "DDR2": "1:2", "DDR3": "1:4", "DDR4": "1:4" }[core_config["memtype"]]) from litex.tools.litex_sim import get_sdram_phy_settings sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings phy_settings = get_sdram_phy_settings( memtype=sdram_module.memtype, data_width=core_config["sdram_module_nb"] * 8, clk_freq=sdram_clk_freq) self.submodules.ddrphy = SDRAMPHYModel( module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=3, ) class ControllerDynamicSettings(Module, AutoCSR, AutoDoc): """Allows to change LiteDRAMController behaviour at runtime""" def __init__(self): self.refresh = CSRStorage( reset=1, description="Enable/disable Refresh commands sending") self.submodules.controller_settings = ControllerDynamicSettings() self.add_csr("controller_settings") controller_settings = ControllerSettings() controller_settings.with_auto_precharge = True controller_settings.with_refresh = self.controller_settings.refresh.storage self.add_csr("ddrphy") self.add_sdram( "sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=0, l2_cache_min_data_width=0, #128 l2_cache_reverse=True, controller_settings=controller_settings) # Ethernet / Etherbone --------------------------------------------------------------------- if not args.sim: # Ethernet PHY (arty) self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy, ip_address=ip_address, mac_address=mac_address, udp_port=udp_port) else: # Ethernet PHY (simulation) self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) # FIXME self.add_csr("ethphy") # Ethernet Core ethcore = LiteEthUDPIPCore(self.ethphy, ip_address=ip_address, mac_address=mac_address, clk_freq=sys_clk_freq) self.submodules.ethcore = ethcore # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, udp_port, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds") # Analyzer --------------------------------------------------------------------------------- # analyzer_signals = [ # self.bus.masters['master0'].stb, # self.bus.masters['master0'].cyc, # self.bus.masters['master0'].adr, # self.bus.masters['master0'].we, # self.bus.masters['master0'].ack, # self.bus.masters['master0'].sel, # self.bus.masters['master0'].dat_w, # self.bus.masters['master0'].dat_r, # ] # from litescope import LiteScopeAnalyzer # self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, # depth = 512, # clock_domain = "sys", # csr_csv = "analyzer.csv") # self.add_csr("analyzer") if args.sim: self.comb += platform.trace.eq(1) # Rowhammer -------------------------------------------------------------------------------- from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter self.submodules.rowhammer_dma = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma) self.add_csr("rowhammer") # Bist ------------------------------------------------------------------------------------- if not args.no_memory_bist: from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker def add_xram(self, name, origin, mem): from litex.soc.interconnect import wishbone from litex.soc.integration.soc import SoCRegion ram_bus = wishbone.Interface(data_width=self.bus.data_width) ram = wishbone.SRAM(mem, bus=ram_bus) self.bus.add_slave( name, ram.bus, SoCRegion(origin=origin, size=mem.width * mem.depth, mode='rw')) self.check_if_exists(name) self.logger.info("RAM {} {} {}.".format( colorer(name), colorer("added", color="green"), self.bus.regions[name])) setattr(self.submodules, name, ram) return # ------------------------------ writer ------------------------------------ memory_w0 = Memory(32, 1024) memory_w1 = Memory(32, 1024) memory_w2 = Memory(32, 1024) memory_w3 = Memory(32, 1024) memory_adr = Memory(32, 1024) add_xram(self, name='pattern_w0', mem=memory_w0, origin=0x20000000) add_xram(self, name='pattern_w1', mem=memory_w1, origin=0x21000000) add_xram(self, name='pattern_w2', mem=memory_w2, origin=0x22000000) add_xram(self, name='pattern_w3', mem=memory_w3, origin=0x23000000) add_xram(self, name='pattern_adr', mem=memory_adr, origin=0x24000000) class Writer(Module, AutoCSR): def __init__(self, dram_port, w0_port, w1_port, w2_port, w3_port, adr_port): self.reset = CSRStorage() self.start = CSRStorage() self.done = CSRStatus() self.count = CSRStorage(size=(32 * 1)) self.mem_base = CSRStorage(size=32) self.mem_mask = CSRStorage(size=32) self.data_mask = CSRStorage(size=32) # patterns dma = LiteDRAMDMAWriter(dram_port, fifo_depth=1) self.submodules += dma cmd_counter = Signal(32) self.comb += [ w0_port.adr.eq(cmd_counter & self.data_mask.storage), w1_port.adr.eq(cmd_counter & self.data_mask.storage), w2_port.adr.eq(cmd_counter & self.data_mask.storage), w3_port.adr.eq(cmd_counter & self.data_mask.storage), adr_port.adr.eq(cmd_counter & self.data_mask.storage), ] self.comb += [ dma.sink.address.eq(self.mem_base.storage + adr_port.dat_r + (cmd_counter & self.mem_mask.storage)), dma.sink.data.eq( Cat(w0_port.dat_r, w1_port.dat_r, w2_port.dat_r, w3_port.dat_r)), ] fsm = FSM(reset_state="IDLE") self.submodules += fsm fsm.act( "IDLE", If( self.start.storage, NextValue(cmd_counter, 0), NextState("WAIT"), )) fsm.act( "WAIT", If(cmd_counter >= self.count.storage, NextState("DONE")).Else(NextState("RUN"))) fsm.act( "RUN", dma.sink.valid.eq(1), If(dma.sink.ready, NextValue(cmd_counter, cmd_counter + 1), NextState("WAIT"))) fsm.act("DONE", self.done.status.eq(1), If(self.reset.storage, NextState("IDLE"))) dram_port = self.sdram.crossbar.get_port() w0_port = memory_w0.get_port() w1_port = memory_w1.get_port() w2_port = memory_w2.get_port() w3_port = memory_w3.get_port() adr_port = memory_adr.get_port() self.specials += w0_port, w1_port, w2_port, w3_port, adr_port self.submodules.writer = Writer(dram_port, w0_port, w1_port, w2_port, w3_port, adr_port) self.add_csr('writer') # ----------------------------- reader ------------------------------------- memory_rd_w0 = Memory(32, 1024) memory_rd_w1 = Memory(32, 1024) memory_rd_w2 = Memory(32, 1024) memory_rd_w3 = Memory(32, 1024) memory_rd_adr = Memory(32, 1024) add_xram(self, name='pattern_rd_w0', mem=memory_rd_w0, origin=0x30000000) add_xram(self, name='pattern_rd_w1', mem=memory_rd_w1, origin=0x31000000) add_xram(self, name='pattern_rd_w2', mem=memory_rd_w2, origin=0x32000000) add_xram(self, name='pattern_rd_w3', mem=memory_rd_w3, origin=0x33000000) add_xram(self, name='pattern_rd_adr', mem=memory_rd_adr, origin=0x34000000) class Reader(Module, AutoCSR): def __init__(self, dram_port, w0_port, w1_port, w2_port, w3_port, adr_port): self.reset = CSRStorage() self.start = CSRStorage() self.done = CSRStatus() self.count = CSRStorage(size=32) self.pointer = CSRStatus(size=32) self.mem_base = CSRStorage(size=32) self.mem_mask = CSRStorage(size=32) self.data_mask = CSRStorage(size=32) # patterns dma = LiteDRAMDMAReader(dram_port, fifo_depth=1, fifo_buffered=False) self.submodules += dma cmd_counter = Signal(32) self.comb += [ w0_port.adr.eq(cmd_counter & self.data_mask.storage), w1_port.adr.eq(cmd_counter & self.data_mask.storage), w2_port.adr.eq(cmd_counter & self.data_mask.storage), w3_port.adr.eq(cmd_counter & self.data_mask.storage), adr_port.adr.eq(cmd_counter & self.data_mask.storage), ] data_pattern = Signal(32 * 4) self.comb += [ dma.sink.address.eq(self.mem_base.storage + adr_port.dat_r + (cmd_counter & self.mem_mask.storage)), data_pattern.eq( Cat(w0_port.dat_r, w1_port.dat_r, w2_port.dat_r, w3_port.dat_r)), ] fsm = FSM(reset_state="IDLE") self.submodules += fsm fsm.act( "IDLE", If( self.start.storage, NextValue(cmd_counter, 0), NextValue(self.pointer.status, 0xdeadbeef), NextState("WAIT"), )) fsm.act( "WAIT", If(cmd_counter >= self.count.storage, NextState("DONE")).Else(NextState("WR_ADR"))) fsm.act("WR_ADR", dma.sink.valid.eq(1), If(dma.sink.ready, NextState("RD_DATA"))) fsm.act( "RD_DATA", dma.source.ready.eq(1), If( dma.source.valid, NextValue(cmd_counter, cmd_counter + 1), If(dma.source.data != data_pattern, NextValue(self.pointer.status, cmd_counter)), NextState("WAIT"))) fsm.act("DONE", self.done.status.eq(1), If(self.reset.storage, NextState("IDLE"))) dram_rd_port = self.sdram.crossbar.get_port() w0_port = memory_rd_w0.get_port() w1_port = memory_rd_w1.get_port() w2_port = memory_rd_w2.get_port() w3_port = memory_rd_w3.get_port() adr_port = memory_rd_adr.get_port() self.specials += w0_port, w1_port, w2_port, w3_port, adr_port self.submodules.reader = Reader(dram_rd_port, w0_port, w1_port, w2_port, w3_port, adr_port) self.add_csr('reader')
def __init__(self, platform, core_config, **kwargs): platform.add_extension(get_common_ios()) # Parameters ------------------------------------------------------------------------------- sys_clk_freq = core_config["sys_clk_freq"] cpu_type = core_config["cpu"] csr_expose = core_config.get("csr_expose", False) csr_align = core_config.get("csr_align", 32) if cpu_type is None: kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 0 kwargs["l2_size"] = 0 kwargs["min_l2_data_width"] = 0 kwargs["with_uart"] = False kwargs["with_timer"] = False kwargs["with_ctrl"] = False kwargs["with_wishbone"] = False else: kwargs["l2_size"] = 0 kwargs["min_l2_data_width"] = 0 # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, sys_clk_freq, cpu_type=cpu_type, csr_alignment=csr_align, max_sdram_size= 0x01000000, # Only expose 16MB to the CPU, enough for Init/Calib. **kwargs) # CRG -------------------------------------------------------------------------------------- if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: self.submodules.crg = crg = LiteDRAMECP5DDRPHYCRG( platform, core_config) if core_config["sdram_phy"] in [ litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY ]: self.submodules.crg = LiteDRAMS7DDRPHYCRG(platform, core_config) # DRAM ------------------------------------------------------------------------------------- platform.add_extension(get_dram_ios(core_config)) if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: assert core_config["memtype"] in ["DDR3"] self.submodules.ddrphy = core_config["sdram_phy"]( pads=platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.comb += crg.stop.eq(self.ddrphy.init.stop) sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2") if core_config["sdram_phy"] in [ litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY ]: assert core_config["memtype"] in ["DDR2", "DDR3"] self.submodules.ddrphy = core_config["sdram_phy"]( pads=platform.request("ddram"), memtype=core_config["memtype"], nphases=4 if core_config["memtype"] == "DDR3" else 2, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=core_config["iodelay_clk_freq"], cmd_latency=core_config["cmd_latency"]) self.add_constant("CMD_DELAY", core_config["cmd_delay"]) if core_config["memtype"] == "DDR3": self.ddrphy.settings.add_electrical_settings( rtt_nom=core_config["rtt_nom"], rtt_wr=core_config["rtt_wr"], ron=core_config["ron"]) self.add_csr("ddrphy") sdram_module = core_config["sdram_module"]( sys_clk_freq, "1:4" if core_config["memtype"] == "DDR3" else "1:2") controller_settings = controller_settings = ControllerSettings( cmd_buffer_depth=core_config["cmd_buffer_depth"]) self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings, controller_settings=controller_settings) # DRAM Initialization ---------------------------------------------------------------------- self.submodules.ddrctrl = LiteDRAMCoreControl() self.add_csr("ddrctrl") self.comb += [ platform.request("init_done").eq(self.ddrctrl.init_done.storage), platform.request("init_error").eq(self.ddrctrl.init_error.storage) ] # CSR port --------------------------------------------------------------------------------- if csr_expose: csr_port = csr_bus.Interface(address_width=self.csr_address_width, data_width=self.csr_data_width) self.add_csr_master(csr_port) platform.add_extension( get_csr_ios(self.csr_address_width, self.csr_data_width)) _csr_port_io = platform.request("csr_port", 0) self.comb += [ csr_port.adr.eq(_csr_port_io.adr), csr_port.we.eq(_csr_port_io.we), csr_port.dat_w.eq(_csr_port_io.dat_w), _csr_port_io.dat_r.eq(csr_port.dat_r), ] if self.cpu_type == None: csr_base = core_config.get("csr_base", 0) self.shadow_base = csr_base # User ports ------------------------------------------------------------------------------- self.comb += [ platform.request("user_clk").eq(ClockSignal()), platform.request("user_rst").eq(ResetSignal()) ] for name, port in core_config["user_ports"].items(): # Native ------------------------------------------------------------------------------- if port["type"] == "native": user_port = self.sdram.crossbar.get_port() platform.add_extension( get_native_user_port_ios(name, user_port.address_width, user_port.data_width)) _user_port_io = platform.request("user_port_{}".format(name)) self.comb += [ # cmd user_port.cmd.valid.eq(_user_port_io.cmd_valid), _user_port_io.cmd_ready.eq(user_port.cmd.ready), user_port.cmd.we.eq(_user_port_io.cmd_we), user_port.cmd.addr.eq(_user_port_io.cmd_addr), # wdata user_port.wdata.valid.eq(_user_port_io.wdata_valid), _user_port_io.wdata_ready.eq(user_port.wdata.ready), user_port.wdata.we.eq(_user_port_io.wdata_we), user_port.wdata.data.eq(_user_port_io.wdata_data), # rdata _user_port_io.rdata_valid.eq(user_port.rdata.valid), user_port.rdata.ready.eq(_user_port_io.rdata_ready), _user_port_io.rdata_data.eq(user_port.rdata.data), ] # Wishbone ----------------------------------------------------------------------------- elif port["type"] == "wishbone": user_port = self.sdram.crossbar.get_port() wb_port = wishbone.Interface(user_port.data_width, user_port.address_width) wishbone2native = LiteDRAMWishbone2Native(wb_port, user_port) self.submodules += wishbone2native platform.add_extension( get_wishbone_user_port_ios(name, len(wb_port.adr), len(wb_port.dat_w))) _wb_port_io = platform.request("user_port_{}".format(name)) self.comb += [ wb_port.adr.eq(_wb_port_io.adr), wb_port.dat_w.eq(_wb_port_io.dat_w), _wb_port_io.dat_r.eq(wb_port.dat_r), wb_port.sel.eq(_wb_port_io.sel), wb_port.cyc.eq(_wb_port_io.cyc), wb_port.stb.eq(_wb_port_io.stb), _wb_port_io.ack.eq(wb_port.ack), wb_port.we.eq(_wb_port_io.we), _wb_port_io.err.eq(wb_port.err), ] # AXI ---------------------------------------------------------------------------------- elif port["type"] == "axi": user_port = self.sdram.crossbar.get_port() axi_port = LiteDRAMAXIPort( user_port.data_width, user_port.address_width + log2_int(user_port.data_width // 8), port["id_width"]) axi2native = LiteDRAMAXI2Native(axi_port, user_port) self.submodules += axi2native platform.add_extension( get_axi_user_port_ios(name, axi_port.address_width, axi_port.data_width, port["id_width"])) _axi_port_io = platform.request("user_port_{}".format(name)) self.comb += [ # aw axi_port.aw.valid.eq(_axi_port_io.awvalid), _axi_port_io.awready.eq(axi_port.aw.ready), axi_port.aw.addr.eq(_axi_port_io.awaddr), axi_port.aw.burst.eq(_axi_port_io.awburst), axi_port.aw.len.eq(_axi_port_io.awlen), axi_port.aw.size.eq(_axi_port_io.awsize), axi_port.aw.id.eq(_axi_port_io.awid), # w axi_port.w.valid.eq(_axi_port_io.wvalid), _axi_port_io.wready.eq(axi_port.w.ready), axi_port.w.last.eq(_axi_port_io.wlast), axi_port.w.strb.eq(_axi_port_io.wstrb), axi_port.w.data.eq(_axi_port_io.wdata), # b _axi_port_io.bvalid.eq(axi_port.b.valid), axi_port.b.ready.eq(_axi_port_io.bready), _axi_port_io.bresp.eq(axi_port.b.resp), _axi_port_io.bid.eq(axi_port.b.id), # ar axi_port.ar.valid.eq(_axi_port_io.arvalid), _axi_port_io.arready.eq(axi_port.ar.ready), axi_port.ar.addr.eq(_axi_port_io.araddr), axi_port.ar.burst.eq(_axi_port_io.arburst), axi_port.ar.len.eq(_axi_port_io.arlen), axi_port.ar.size.eq(_axi_port_io.arsize), axi_port.ar.id.eq(_axi_port_io.arid), # r _axi_port_io.rvalid.eq(axi_port.r.valid), axi_port.r.ready.eq(_axi_port_io.rready), _axi_port_io.rlast.eq(axi_port.r.last), _axi_port_io.rresp.eq(axi_port.r.resp), _axi_port_io.rdata.eq(axi_port.r.data), _axi_port_io.rid.eq(axi_port.r.id), ] # FIFO --------------------------------------------------------------------------------- elif port["type"] == "fifo": platform.add_extension( get_fifo_user_port_ios(name, user_port.data_width)) _user_fifo_io = platform.request("user_fifo_{}".format(name)) fifo = LiteDRAMFIFO( data_width=user_port.data_width, base=port["base"], depth=port["depth"], write_port=self.sdram.crossbar.get_port("write"), write_threshold=port["depth"] - 32, # FIXME read_port=self.sdram.crossbar.get_port("read"), read_threshold=32 # FIXME ) self.submodules += fifo self.comb += [ # in fifo.sink.valid.eq(_user_fifo_io.in_valid), _user_fifo_io.in_ready.eq(fifo.sink.ready), fifo.sink.data.eq(_user_fifo_io.in_data), # out _user_fifo_io.out_valid.eq(fifo.source.valid), fifo.source.ready.eq(_user_fifo_io.out_ready), _user_fifo_io.out_data.eq(fifo.source.data), ] else: raise ValueError("Unsupported port type: {}".format( port["type"]))
def __init__(self, platform, with_sdram_bist=True, bist_async=True, bist_random=True, spiflash="spiflash_1x", **kwargs): clk_freq = 100*1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, with_uart=False, **kwargs) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() self.submodules.leds = led.ClassicLed(Cat(platform.request("user_led", i) for i in range(4))) self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds")) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 6) sdram_module = MT41K128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(cmd_buffer_depth=8)) # sdram bist if with_sdram_bist: generator_user_port = self.sdram.crossbar.get_port(mode="write", cd="clk50" if bist_async else "sys") self.submodules.generator = LiteDRAMBISTGenerator(generator_user_port, random=bist_random) checker_user_port = self.sdram.crossbar.get_port(mode="read", cd="clk50" if bist_async else "sys") self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random) # spi flash spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=spiflash_dummy[spiflash], div=2) self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region("spiflash", self.mem_map["spiflash"] | self.shadow_base, 16*1024*1024) # uart mux uart_sel = platform.request("user_sw", 0) self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200) uart_phys = { "cpu": UARTVirtualPhy(), "bridge": UARTVirtualPhy() } self.comb += [ If(uart_sel, self.uart_phy.source.connect(uart_phys["bridge"].source), uart_phys["bridge"].sink.connect(self.uart_phy.sink), uart_phys["cpu"].source.ready.eq(1) # avoid stalling cpu ).Else( self.uart_phy.source.connect(uart_phys["cpu"].source), uart_phys["cpu"].sink.connect(self.uart_phy.sink), uart_phys["bridge"].source.ready.eq(1) # avoid stalling bridge ) ] # uart cpu self.submodules.uart = UART(uart_phys["cpu"]) # uart bridge self.submodules.bridge = WishboneStreamingBridge(uart_phys["bridge"], self.clk_freq) self.add_wb_master(self.bridge.wishbone)
def __init__(self, sys_clk_freq=int(100e6), cpu_count=1, with_ethernet=False, with_analyzer=False, **kwargs): VexRiscvSMP.litedram_width = 128 VexRiscvSMP.ibus_width = 64 VexRiscvSMP.dbus_width = 64 VexRiscvSMP.coherent_dma = True platform = arty.Platform() platform.add_extension(arty._sdcard_pmod_io) # MicroSD PMOD on JD. platform.add_extension(arty._usb_uart_pmod_io) # USB UART PMOD on JA. # SoCCore ---------------------------------------------------------------------------------- kwargs["integrated_rom_size"] = 0x10000 kwargs["csr_data_width"] = 8 SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_cls=VexRiscvSMP, cpu_variant="default", **kwargs) self.add_constant("config_cpu_count", cpu_count) # for dts generation # PLIC ------------------------------------------------------------------------------------ self.bus.add_slave("plic", self.cpu.plicbus, region=SoCRegion(origin=0xf0C00000, size=0x400000, cached=False)) # CLINT ------------------------------------------------------------------------------------ self.bus.add_slave("clint", self.cpu.cbus, region=SoCRegion(origin=0xf0010000, size=0x10000, cached=False)) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True, controller_settings=ControllerSettings( cmd_buffer_buffered=False, with_auto_precharge=False)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # JTAG --------------------------------------------------------------------------------- self.submodules.jtag = S7JTAG() self.comb += self.cpu.jtag_clk.eq(self.jtag.tck) self.comb += self.cpu.jtag_enable.eq(1) self.comb += self.cpu.jtag_capture.eq(self.jtag.capture) self.comb += self.cpu.jtag_shift.eq(self.jtag.shift) self.comb += self.cpu.jtag_update.eq(self.jtag.update) self.comb += self.cpu.jtag_reset.eq(self.jtag.reset) self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi) self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: from litescope import LiteScopeAnalyzer self.add_uartbone("usb_uart") analyzer_signals = [self.cpu.dma_buses[0]] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=512, clock_domain="sys", csr_csv="analyzer.csv") self.add_csr("analyzer")
def __init__(self, platform, core_config, **kwargs): platform.add_extension(get_common_ios()) sys_clk_freq = core_config["sys_clk_freq"] SoCSDRAM.__init__( self, platform, sys_clk_freq, cpu_type=core_config["cpu"], l2_size=32 * core_config["sdram_module_nb"], reserve_nmi_interrupt=False, csr_data_width=8 if core_config["cpu"] is not None else 32, with_uart=core_config["cpu"] is not None, with_timer=core_config["cpu"] is not None, csr_expose=True, **kwargs) # crg self.submodules.crg = LiteDRAMCRG(platform, core_config) # sdram platform.add_extension(get_dram_ios(core_config)) self.submodules.ddrphy = core_config["sdram_phy"]( platform.request("ddram"), sys_clk_freq=sys_clk_freq, iodelay_clk_freq=core_config["iodelay_clk_freq"]) self.ddrphy.settings.add_electrical_settings( rtt_nom=core_config["rtt_nom"], rtt_wr=core_config["rtt_wr"], ron=core_config["ron"]) sdram_module = core_config["sdram_module"]( sys_clk_freq, "1:4", speedgrade=core_config["sdram_module_speedgrade"]) controller_settings = controller_settings = ControllerSettings( cmd_buffer_depth=core_config["cmd_buffer_depth"], read_time=core_config["read_time"], write_time=core_config["write_time"]) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # sdram init self.submodules.ddrctrl = LiteDRAMCoreControl() self.add_constant("DDRPHY_HIGH_SKEW_DISABLE", None) self.comb += [ platform.request("init_done").eq(self.ddrctrl.init_done.storage), platform.request("init_error").eq(self.ddrctrl.init_error.storage) ] # user port self.comb += [ platform.request("user_clk").eq(ClockSignal()), platform.request("user_rst").eq(ResetSignal()) ] if core_config["user_ports_type"] == "native": for i in range(core_config["user_ports_nb"]): user_port = self.sdram.crossbar.get_port() platform.add_extension( get_native_user_port_ios(i, user_port.address_width, user_port.data_width)) _user_port_io = platform.request("user_port", i) self.comb += [ # cmd user_port.cmd.valid.eq(_user_port_io.cmd_valid), _user_port_io.cmd_ready.eq(user_port.cmd.ready), user_port.cmd.we.eq(_user_port_io.cmd_we), user_port.cmd.addr.eq(_user_port_io.cmd_addr), # wdata user_port.wdata.valid.eq(_user_port_io.wdata_valid), _user_port_io.wdata_ready.eq(user_port.wdata.ready), user_port.wdata.we.eq(_user_port_io.wdata_we), user_port.wdata.data.eq(_user_port_io.wdata_data), # rdata _user_port_io.rdata_valid.eq(user_port.rdata.valid), user_port.rdata.ready.eq(_user_port_io.rdata_ready), _user_port_io.rdata_data.eq(user_port.rdata.data), ] elif core_config["user_ports_type"] == "axi": for i in range(core_config["user_ports_nb"]): user_port = self.sdram.crossbar.get_port() axi_port = LiteDRAMAXIPort( user_port.data_width, user_port.address_width + log2_int(user_port.data_width // 8), core_config["user_ports_id_width"]) axi2native = LiteDRAMAXI2Native(axi_port, user_port) self.submodules += axi2native platform.add_extension( get_axi_user_port_ios(i, axi_port.address_width, axi_port.data_width, core_config["user_ports_id_width"])) _axi_port_io = platform.request("user_port", i) self.comb += [ # aw axi_port.aw.valid.eq(_axi_port_io.aw_valid), _axi_port_io.aw_ready.eq(axi_port.aw.ready), axi_port.aw.addr.eq(_axi_port_io.aw_addr), axi_port.aw.burst.eq(_axi_port_io.aw_burst), axi_port.aw.len.eq(_axi_port_io.aw_len), axi_port.aw.size.eq(_axi_port_io.aw_size), axi_port.aw.id.eq(_axi_port_io.aw_id), # w axi_port.w.valid.eq(_axi_port_io.w_valid), _axi_port_io.w_ready.eq(axi_port.w.ready), axi_port.w.last.eq(_axi_port_io.w_last), axi_port.w.strb.eq(_axi_port_io.w_strb), axi_port.w.data.eq(_axi_port_io.w_data), # b _axi_port_io.b_valid.eq(axi_port.b.valid), axi_port.b.ready.eq(_axi_port_io.b_ready), _axi_port_io.b_resp.eq(axi_port.b.resp), _axi_port_io.b_id.eq(axi_port.b.id), # ar axi_port.ar.valid.eq(_axi_port_io.ar_valid), _axi_port_io.ar_ready.eq(axi_port.ar.ready), axi_port.ar.addr.eq(_axi_port_io.ar_addr), axi_port.ar.burst.eq(_axi_port_io.ar_burst), axi_port.ar.len.eq(_axi_port_io.ar_len), axi_port.ar.size.eq(_axi_port_io.ar_size), axi_port.ar.id.eq(_axi_port_io.ar_id), # r _axi_port_io.r_valid.eq(axi_port.r.valid), axi_port.r.ready.eq(_axi_port_io.r_ready), _axi_port_io.r_last.eq(axi_port.r.last), _axi_port_io.r_resp.eq(axi_port.r.resp), _axi_port_io.r_data.eq(axi_port.r.data), _axi_port_io.r_id.eq(axi_port.r.id), ] else: raise ValueError("Unsupported port type: {}".format( core_config["user_ports_type"]))
def __init__(self, platform, core_config, **kwargs): platform.add_extension(get_common_ios()) sys_clk_freq = core_config["sys_clk_freq"] SoCSDRAM.__init__(self, platform, sys_clk_freq, cpu_type=core_config["cpu"], l2_size=16 * core_config["sdram_module_nb"], **kwargs) # crg self.submodules.crg = LiteDRAMCRG(platform, core_config) # sdram platform.add_extension(get_dram_ios(core_config)) assert core_config["memtype"] in ["DDR2", "DDR3"] self.submodules.ddrphy = core_config["sdram_phy"]( platform.request("ddram"), memtype=core_config["memtype"], nphases=4 if core_config["memtype"] == "DDR3" else 2, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=core_config["iodelay_clk_freq"], cmd_latency=core_config["cmd_latency"]) self.add_constant("CMD_DELAY", core_config["cmd_delay"]) if core_config["memtype"] == "DDR3": self.ddrphy.settings.add_electrical_settings( rtt_nom=core_config["rtt_nom"], rtt_wr=core_config["rtt_wr"], ron=core_config["ron"]) sdram_module = core_config["sdram_module"]( sys_clk_freq, "1:4" if core_config["memtype"] == "DDR3" else "1:2") controller_settings = controller_settings = ControllerSettings( cmd_buffer_depth=core_config["cmd_buffer_depth"]) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # sdram init self.submodules.ddrctrl = LiteDRAMCoreControl() self.comb += [ platform.request("init_done").eq(self.ddrctrl.init_done.storage), platform.request("init_error").eq(self.ddrctrl.init_error.storage) ] # CSR port if core_config.get("expose_csr_port", "no") == "yes": csr_port = csr_bus.Interface(self.csr_address_width, self.csr_data_width) self.add_csr_master(csr_port) platform.add_extension( get_csr_ios(self.csr_address_width, self.csr_data_width)) _csr_port_io = platform.request("csr_port", 0) self.comb += [ csr_port.adr.eq(_csr_port_io.adr), csr_port.we.eq(_csr_port_io.we), csr_port.dat_w.eq(_csr_port_io.dat_w), _csr_port_io.dat_r.eq(csr_port.dat_r), ] # user port self.comb += [ platform.request("user_clk").eq(ClockSignal()), platform.request("user_rst").eq(ResetSignal()) ] if core_config["user_ports_type"] == "native": for i in range(core_config["user_ports_nb"]): user_port = self.sdram.crossbar.get_port() platform.add_extension( get_native_user_port_ios(i, user_port.address_width, user_port.data_width)) _user_port_io = platform.request("user_port", i) self.comb += [ # cmd user_port.cmd.valid.eq(_user_port_io.cmd_valid), _user_port_io.cmd_ready.eq(user_port.cmd.ready), user_port.cmd.we.eq(_user_port_io.cmd_we), user_port.cmd.addr.eq(_user_port_io.cmd_addr), # wdata user_port.wdata.valid.eq(_user_port_io.wdata_valid), _user_port_io.wdata_ready.eq(user_port.wdata.ready), user_port.wdata.we.eq(_user_port_io.wdata_we), user_port.wdata.data.eq(_user_port_io.wdata_data), # rdata _user_port_io.rdata_valid.eq(user_port.rdata.valid), user_port.rdata.ready.eq(_user_port_io.rdata_ready), _user_port_io.rdata_data.eq(user_port.rdata.data), ] elif core_config["user_ports_type"] == "axi": for i in range(core_config["user_ports_nb"]): user_port = self.sdram.crossbar.get_port() axi_port = LiteDRAMAXIPort( user_port.data_width, user_port.address_width + log2_int(user_port.data_width // 8), core_config["user_ports_id_width"]) axi2native = LiteDRAMAXI2Native(axi_port, user_port) self.submodules += axi2native platform.add_extension( get_axi_user_port_ios(i, axi_port.address_width, axi_port.data_width, core_config["user_ports_id_width"])) _axi_port_io = platform.request("user_port", i) self.comb += [ # aw axi_port.aw.valid.eq(_axi_port_io.aw_valid), _axi_port_io.aw_ready.eq(axi_port.aw.ready), axi_port.aw.addr.eq(_axi_port_io.aw_addr), axi_port.aw.burst.eq(_axi_port_io.aw_burst), axi_port.aw.len.eq(_axi_port_io.aw_len), axi_port.aw.size.eq(_axi_port_io.aw_size), axi_port.aw.id.eq(_axi_port_io.aw_id), # w axi_port.w.valid.eq(_axi_port_io.w_valid), _axi_port_io.w_ready.eq(axi_port.w.ready), axi_port.w.last.eq(_axi_port_io.w_last), axi_port.w.strb.eq(_axi_port_io.w_strb), axi_port.w.data.eq(_axi_port_io.w_data), # b _axi_port_io.b_valid.eq(axi_port.b.valid), axi_port.b.ready.eq(_axi_port_io.b_ready), _axi_port_io.b_resp.eq(axi_port.b.resp), _axi_port_io.b_id.eq(axi_port.b.id), # ar axi_port.ar.valid.eq(_axi_port_io.ar_valid), _axi_port_io.ar_ready.eq(axi_port.ar.ready), axi_port.ar.addr.eq(_axi_port_io.ar_addr), axi_port.ar.burst.eq(_axi_port_io.ar_burst), axi_port.ar.len.eq(_axi_port_io.ar_len), axi_port.ar.size.eq(_axi_port_io.ar_size), axi_port.ar.id.eq(_axi_port_io.ar_id), # r _axi_port_io.r_valid.eq(axi_port.r.valid), axi_port.r.ready.eq(_axi_port_io.r_ready), _axi_port_io.r_last.eq(axi_port.r.last), _axi_port_io.r_resp.eq(axi_port.r.resp), _axi_port_io.r_data.eq(axi_port.r.data), _axi_port_io.r_id.eq(axi_port.r.id), ] else: raise ValueError("Unsupported port type: {}".format( core_config["user_ports_type"]))
def __init__(self, cpu_count, init_memories=False, with_sdcard=False): # Cluster configs --------------------------------------------------------------------- VexRiscvSMP.litedram_width = 128 VexRiscvSMP.ibus_width = 64 VexRiscvSMP.dbus_width = 64 VexRiscvSMP.coherent_dma = with_sdcard # ------------------------------------------------------------------------------------------- platform = Platform() sys_clk_freq = int(1e6) sdram_init = [] if init_memories: sdram_init = get_mem_data( { "images/fw_jump.bin": "0x00f00000", "images/Image": "0x00000000", "images/dtb": "0x00ef0000", "images/rootfs.cpio": "0x01000000", }, "little") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="default", cpu_cls=VexRiscvSMP, uart_name="sim", integrated_rom_size=0x10000, integrated_main_ram_size=0x00000000) self.platform.name = "sim" self.add_constant("SIM") self.add_constant("config_cpu_count", cpu_count) # for dts generation # PLIC ------------------------------------------------------------------------------------ self.bus.add_slave("plic", self.cpu.plicbus, region=SoCRegion(origin=0xf0C00000, size=0x400000, cached=False)) interrupt_map = { **SoCCore.interrupt_map, **{ "uart": 1, } } # CLINT ------------------------------------------------------------------------------------ self.bus.add_slave("clint", self.cpu.cbus, region=SoCRegion(origin=0xf0010000, size=0x10000, cached=False)) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # SDRAM ------------------------------------------------------------------------------------ phy_settings = get_sdram_phy_settings(memtype="DDR3", data_width=16, clk_freq=100e6) self.submodules.sdrphy = SDRAMPHYModel(module=MT41K128M16( 100e6, "1:4"), settings=phy_settings, clk_freq=100e6, init=sdram_init) self.add_sdram( "sdram", phy=self.sdrphy, module=MT41K128M16(100e6, "1:4"), origin=self.mem_map["main_ram"], controller_settings=ControllerSettings(cmd_buffer_buffered=False, with_auto_precharge=True)) if init_memories: self.add_constant("MEMTEST_BUS_SIZE", 0) # Skip test if memory is initialized to avoid self.add_constant("MEMTEST_ADDR_SIZE", 0) # corrumpting the content. self.add_constant("MEMTEST_DATA_SIZE", 0) self.add_constant("ROM_BOOT_ADDRESS", 0x40f00000) # Jump to fw_jump.bin else: self.add_constant("MEMTEST_BUS_SIZE", 4096) self.add_constant("MEMTEST_ADDR_SIZE", 4096) self.add_constant("MEMTEST_DATA_SIZE", 4096) # SDCard ----------------------------------------------------------------------------------- if with_sdcard: self.add_sdcard("sdcard", use_emulator=True)
def __init__(self, platform, with_sdram_bist=True, bist_async=True, bist_random=True, spiflash="spiflash_1x", **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, with_uart=False, **kwargs) self.submodules.crg = CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() uart_interfaces = [RS232PHYInterface() for i in range(2)] self.submodules.uart = UART(uart_interfaces[0]) self.submodules.bridge = WishboneStreamingBridge( uart_interfaces[1], self.clk_freq) self.add_wb_master(self.bridge.wishbone) self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200) self.submodules.uart_multiplexer = UARTMultiplexer( uart_interfaces, self.uart_phy) self.comb += self.uart_multiplexer.sel.eq( platform.request("user_sw", 0)) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6)) self.submodules.leds = led.ClassicLed( Cat(platform.request("user_led", i) for i in range(4))) self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds")) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 3) self.add_constant("A7DDRPHY_DELAY", 14) sdram_module = MT41K128M16(self.clk_freq, "1:4") self.register_sdram( self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(cmd_buffer_depth=8)) # sdram bist if with_sdram_bist: generator_user_port = self.sdram.crossbar.get_port( mode="write", cd="clk50" if bist_async else "sys") self.submodules.generator = LiteDRAMBISTGenerator( generator_user_port, random=bist_random) checker_user_port = self.sdram.crossbar.get_port( mode="read", cd="clk50" if bist_async else "sys") self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random) # spi flash spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=2) self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region("spiflash", self.mem_map["spiflash"] | self.shadow_base, 16 * 1024 * 1024)
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), args=None, ip_address="192.168.100.50", mac_address=0x10e2d5000001, udp_port=1234, **kwargs): if not args.sim: platform = arty.Platform(toolchain=toolchain) else: platform = SimPlatform("SIM", _io) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- if not args.sim: self.submodules.crg = _CRG(platform, sys_clk_freq, args) else: self.submodules.crg = CRG(platform.request("sys_clk")) # DDR3 SDRAM ------------------------------------------------------------------------------- if not args.sim: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) else: from litedram.gen import get_dram_ios core_config = dict() core_config["sdram_module_nb"] = 2 # Number of byte groups core_config["sdram_rank_nb"] = 1 # Number of ranks core_config['sdram_module'] = getattr(litedram_modules, 'MT41K128M16') core_config["memtype"] = "DDR3" # DRAM type platform.add_extension(get_dram_ios(core_config)) sdram_module = core_config["sdram_module"]( sys_clk_freq, rate={ "DDR2": "1:2", "DDR3": "1:4", "DDR4": "1:4" }[core_config["memtype"]]) from litex.tools.litex_sim import get_sdram_phy_settings sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings phy_settings = get_sdram_phy_settings( memtype=sdram_module.memtype, data_width=core_config["sdram_module_nb"] * 8, clk_freq=sdram_clk_freq) self.submodules.ddrphy = SDRAMPHYModel( module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=3, ) class ControllerDynamicSettings(Module, AutoCSR, AutoDoc): """Allows to change LiteDRAMController behaviour at runtime""" def __init__(self): self.refresh = CSRStorage( reset=1, description="Enable/disable Refresh commands sending") self.submodules.controller_settings = ControllerDynamicSettings() self.add_csr("controller_settings") controller_settings = ControllerSettings() controller_settings.with_auto_precharge = True controller_settings.with_refresh = self.controller_settings.refresh.storage self.add_csr("ddrphy") self.add_sdram( "sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=0, l2_cache_min_data_width=0, #128 l2_cache_reverse=True, controller_settings=controller_settings) # Ethernet / Etherbone --------------------------------------------------------------------- if not args.sim: # Ethernet PHY (arty) self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy, ip_address=ip_address, mac_address=mac_address, udp_port=udp_port) else: # Ethernet PHY (simulation) self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) # FIXME self.add_csr("ethphy") # Ethernet Core ethcore = LiteEthUDPIPCore(self.ethphy, ip_address=ip_address, mac_address=mac_address, clk_freq=sys_clk_freq) self.submodules.ethcore = ethcore # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, udp_port, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds") if args.sim: self.comb += platform.trace.eq(1) # Rowhammer -------------------------------------------------------------------------------- self.submodules.rowhammer_dma = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma) self.add_csr("rowhammer") def add_xram(self, name, origin, mem, mode='rw'): from litex.soc.interconnect import wishbone from litex.soc.integration.soc import SoCRegion ram = wishbone.SRAM(mem, bus=wishbone.Interface(data_width=mem.width), read_only='w' not in mode) ram_bus = wishbone.Interface(data_width=self.bus.data_width) self.submodules += wishbone.Converter(ram_bus, ram.bus) region = SoCRegion(origin=origin, size=mem.width // 8 * mem.depth, mode=mode) self.bus.add_slave(name, ram_bus, region) self.check_if_exists(name) self.logger.info("RAM {} {} {}.".format( colorer(name), colorer("added", color="green"), self.bus.regions[name])) setattr(self.submodules, name, ram) # Bist ------------------------------------------------------------------------------------- if not args.no_memory_bist: # ------------------------------ writer ------------------------------------ dram_wr_port = self.sdram.crossbar.get_port() self.submodules.writer = Writer(dram_wr_port) self.add_csr('writer') # TODO: Rename as 'pattern_wr_w?' add_xram(self, name='pattern_w0', mem=self.writer.memory_w0, origin=0x20000000) add_xram(self, name='pattern_w1', mem=self.writer.memory_w1, origin=0x21000000) add_xram(self, name='pattern_w2', mem=self.writer.memory_w2, origin=0x22000000) add_xram(self, name='pattern_w3', mem=self.writer.memory_w3, origin=0x23000000) add_xram(self, name='pattern_adr', mem=self.writer.memory_adr, origin=0x24000000) # ----------------------------- reader ------------------------------------- dram_rd_port = self.sdram.crossbar.get_port() self.submodules.reader = Reader(dram_rd_port) self.add_csr('reader') add_xram(self, name='pattern_rd_w0', mem=self.reader.memory_w0, origin=0x30000000) add_xram(self, name='pattern_rd_w1', mem=self.reader.memory_w1, origin=0x31000000) add_xram(self, name='pattern_rd_w2', mem=self.reader.memory_w2, origin=0x32000000) add_xram(self, name='pattern_rd_w3', mem=self.reader.memory_w3, origin=0x33000000) add_xram(self, name='pattern_rd_adr', mem=self.reader.memory_adr, origin=0x34000000) # Payload executor ------------------------------------------------------------------------- if not args.no_payload_executor: # TODO: disconnect bus during payload execution phy_settings = self.sdram.controller.settings.phy scratchpad_width = phy_settings.dfi_databits * phy_settings.nphases scratchpad_size = 2**10 payload_mem = Memory(32, 2**10) scratchpad_mem = Memory(scratchpad_width, scratchpad_size // (scratchpad_width // 8)) self.specials += payload_mem, scratchpad_mem add_xram(self, name='payload', mem=payload_mem, origin=0x35000000) add_xram(self, name='scratchpad', mem=scratchpad_mem, origin=0x36000000, mode='r') self.submodules.payload_executor = PayloadExecutor( mem_payload=payload_mem, mem_scratchpad=scratchpad_mem, dfi=self.sdram.dfii.ext_dfi, dfi_sel=self.sdram.dfii.ext_dfi_sel, nranks=self.sdram.controller.settings.phy.nranks, bankbits=self.sdram.controller.settings.geom.bankbits, rowbits=self.sdram.controller.settings.geom.rowbits, colbits=self.sdram.controller.settings.geom.colbits, rdphase=self.sdram.controller.settings.phy.rdphase, ) self.payload_executor.add_csrs() self.add_csr('payload_executor')
def __init__(self, platform, core_config, **kwargs): platform.add_extension(get_common_ios()) # Parameters ------------------------------------------------------------------------------- sys_clk_freq = core_config["sys_clk_freq"] cpu_type = core_config["cpu"] csr_expose = core_config.get("csr_expose", False) csr_align = core_config.get("csr_align", 32) if cpu_type is None: kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 0 kwargs["l2_size"] = 0 kwargs["with_uart"] = False kwargs["with_timer"] = False kwargs["with_ctrl"] = False kwargs["with_wishbone"] = (cpu_type != None) else: kwargs["l2_size"] = 0 # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, cpu_type=cpu_type, csr_alignment=csr_align, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = LiteDRAMCRG(platform, core_config) # DRAM ------------------------------------------------------------------------------------- platform.add_extension(get_dram_ios(core_config)) assert core_config["memtype"] in ["DDR2", "DDR3"] self.submodules.ddrphy = core_config["sdram_phy"]( platform.request("ddram"), memtype=core_config["memtype"], nphases=4 if core_config["memtype"] == "DDR3" else 2, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=core_config["iodelay_clk_freq"], cmd_latency=core_config["cmd_latency"]) self.add_constant("CMD_DELAY", core_config["cmd_delay"]) if core_config["memtype"] == "DDR3": self.ddrphy.settings.add_electrical_settings( rtt_nom=core_config["rtt_nom"], rtt_wr=core_config["rtt_wr"], ron=core_config["ron"]) sdram_module = core_config["sdram_module"](sys_clk_freq, "1:4" if core_config["memtype"] == "DDR3" else "1:2") controller_settings = controller_settings=ControllerSettings( cmd_buffer_depth=core_config["cmd_buffer_depth"]) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # DRAM Initialization ---------------------------------------------------------------------- self.submodules.ddrctrl = LiteDRAMCoreControl() self.comb += [ platform.request("init_done").eq(self.ddrctrl.init_done.storage), platform.request("init_error").eq(self.ddrctrl.init_error.storage) ] # CSR port --------------------------------------------------------------------------------- if csr_expose: csr_port = csr_bus.Interface( address_width=self.csr_address_width, data_width=self.csr_data_width) self.add_csr_master(csr_port) platform.add_extension(get_csr_ios(self.csr_address_width, self.csr_data_width)) _csr_port_io = platform.request("csr_port", 0) self.comb += [ csr_port.adr.eq(_csr_port_io.adr), csr_port.we.eq(_csr_port_io.we), csr_port.dat_w.eq(_csr_port_io.dat_w), _csr_port_io.dat_r.eq(csr_port.dat_r), ] if self.cpu_type == None: csr_base = core_config.get("csr_base", 0) self.shadow_base = csr_base; # User ports ------------------------------------------------------------------------------- self.comb += [ platform.request("user_clk").eq(ClockSignal()), platform.request("user_rst").eq(ResetSignal()) ] if core_config["user_ports_type"] == "native": for i in range(core_config["user_ports_nb"]): user_port = self.sdram.crossbar.get_port() platform.add_extension(get_native_user_port_ios(i, user_port.address_width, user_port.data_width)) _user_port_io = platform.request("user_port", i) self.comb += [ # cmd user_port.cmd.valid.eq(_user_port_io.cmd_valid), _user_port_io.cmd_ready.eq(user_port.cmd.ready), user_port.cmd.we.eq(_user_port_io.cmd_we), user_port.cmd.addr.eq(_user_port_io.cmd_addr), # wdata user_port.wdata.valid.eq(_user_port_io.wdata_valid), _user_port_io.wdata_ready.eq(user_port.wdata.ready), user_port.wdata.we.eq(_user_port_io.wdata_we), user_port.wdata.data.eq(_user_port_io.wdata_data), # rdata _user_port_io.rdata_valid.eq(user_port.rdata.valid), user_port.rdata.ready.eq(_user_port_io.rdata_ready), _user_port_io.rdata_data.eq(user_port.rdata.data), ] elif core_config["user_ports_type"] == "wishbone": for i in range(core_config["user_ports_nb"]): user_port = self.sdram.crossbar.get_port() wb_port = wishbone.Interface( user_port.data_width, user_port.address_width) wishbone2native = LiteDRAMWishbone2Native(wb_port, user_port) self.submodules += wishbone2native platform.add_extension(get_wishbone_user_port_ios(i, len(wb_port.adr), len(wb_port.dat_w))) _wb_port_io = platform.request("user_port", i) self.comb += [ wb_port.adr.eq(_wb_port_io.adr), wb_port.dat_w.eq(_wb_port_io.dat_w), _wb_port_io.dat_r.eq(wb_port.dat_r), wb_port.sel.eq(_wb_port_io.sel), wb_port.cyc.eq(_wb_port_io.cyc), wb_port.stb.eq(_wb_port_io.stb), _wb_port_io.ack.eq(wb_port.ack), wb_port.we.eq(_wb_port_io.we), _wb_port_io.err.eq(wb_port.err), ] elif core_config["user_ports_type"] == "axi": for i in range(core_config["user_ports_nb"]): user_port = self.sdram.crossbar.get_port() axi_port = LiteDRAMAXIPort( user_port.data_width, user_port.address_width + log2_int(user_port.data_width//8), core_config["user_ports_id_width"]) axi2native = LiteDRAMAXI2Native(axi_port, user_port) self.submodules += axi2native platform.add_extension(get_axi_user_port_ios(i, axi_port.address_width, axi_port.data_width, core_config["user_ports_id_width"])) _axi_port_io = platform.request("user_port", i) self.comb += [ # aw axi_port.aw.valid.eq(_axi_port_io.aw_valid), _axi_port_io.aw_ready.eq(axi_port.aw.ready), axi_port.aw.addr.eq(_axi_port_io.aw_addr), axi_port.aw.burst.eq(_axi_port_io.aw_burst), axi_port.aw.len.eq(_axi_port_io.aw_len), axi_port.aw.size.eq(_axi_port_io.aw_size), axi_port.aw.id.eq(_axi_port_io.aw_id), # w axi_port.w.valid.eq(_axi_port_io.w_valid), _axi_port_io.w_ready.eq(axi_port.w.ready), axi_port.w.last.eq(_axi_port_io.w_last), axi_port.w.strb.eq(_axi_port_io.w_strb), axi_port.w.data.eq(_axi_port_io.w_data), # b _axi_port_io.b_valid.eq(axi_port.b.valid), axi_port.b.ready.eq(_axi_port_io.b_ready), _axi_port_io.b_resp.eq(axi_port.b.resp), _axi_port_io.b_id.eq(axi_port.b.id), # ar axi_port.ar.valid.eq(_axi_port_io.ar_valid), _axi_port_io.ar_ready.eq(axi_port.ar.ready), axi_port.ar.addr.eq(_axi_port_io.ar_addr), axi_port.ar.burst.eq(_axi_port_io.ar_burst), axi_port.ar.len.eq(_axi_port_io.ar_len), axi_port.ar.size.eq(_axi_port_io.ar_size), axi_port.ar.id.eq(_axi_port_io.ar_id), # r _axi_port_io.r_valid.eq(axi_port.r.valid), axi_port.r.ready.eq(_axi_port_io.r_ready), _axi_port_io.r_last.eq(axi_port.r.last), _axi_port_io.r_resp.eq(axi_port.r.resp), _axi_port_io.r_data.eq(axi_port.r.data), _axi_port_io.r_id.eq(axi_port.r.id), ] else: raise ValueError("Unsupported port type: {}".format(core_config["user_ports_type"]))
def __init__(self, sys_clk_freq=int(125e6), cpu_count=1, with_ethernet=False, **kwargs): VexRiscvSMP.litedram_width = 128 VexRiscvSMP.ibus_width = 64 VexRiscvSMP.dbus_width = 64 VexRiscvSMP.coherent_dma = True platform = genesys2.Platform() # SoCCore ---------------------------------------------------------------------------------- kwargs["integrated_rom_size"] = 0x10000 kwargs["csr_data_width"] = 8 SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_cls=VexRiscvSMP, cpu_variant="default", **kwargs) self.add_constant("config_cpu_count", cpu_count) # for dts generation # PLIC ------------------------------------------------------------------------------------ self.bus.add_slave("plic", self.cpu.plicbus, region=SoCRegion(origin=0xf0C00000, size=0x400000, cached=False)) # CLINT ------------------------------------------------------------------------------------ self.bus.add_slave("clint", self.cpu.cbus, region=SoCRegion(origin=0xf0010000, size=0x10000, cached=False)) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( pads=PHYPadsReducer(platform.request("ddram"), [1, 2]), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, cmd_latency=1) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41J256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True, controller_settings=ControllerSettings( cmd_buffer_buffered=False, with_auto_precharge=False)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # JTAG --------------------------------------------------------------------------------- self.submodules.jtag = S7JTAG() self.comb += self.cpu.jtag_clk.eq(self.jtag.tck) self.comb += self.cpu.jtag_enable.eq(1) self.comb += self.cpu.jtag_capture.eq(self.jtag.capture) self.comb += self.cpu.jtag_shift.eq(self.jtag.shift) self.comb += self.cpu.jtag_update.eq(self.jtag.update) self.comb += self.cpu.jtag_reset.eq(self.jtag.reset) self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi) self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, cpu_variant="1c", **kwargs): platform = arty.Platform() platform.add_extension(arty._sdcard_pmod_io) # MicroSD PMOD on JB. # SoCCore ---------------------------------------------------------------------------------- kwargs["integrated_rom_size"] = 0x10000 SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_cls=VexRiscvSMP, cpu_variant=cpu_variant, **kwargs) # PLIC ------------------------------------------------------------------------------------ self.bus.add_slave("plic", self.cpu.plicbus, region=SoCRegion(origin=0xf0C00000, size=0x400000, cached=False)) # CLINT ------------------------------------------------------------------------------------ self.bus.add_slave("clint", self.cpu.cbus, region=SoCRegion(origin=0xf0010000, size=0x10000, cached=False)) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True, controller_settings=ControllerSettings( cmd_buffer_buffered=False, with_auto_precharge=False)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # JTAG --------------------------------------------------------------------------------- self.submodules.jtag = S7JTAG() self.comb += self.cpu.jtag_clk.eq(self.jtag.tck) self.comb += self.cpu.jtag_enable.eq(1) self.comb += self.cpu.jtag_capture.eq(self.jtag.capture) self.comb += self.cpu.jtag_shift.eq(self.jtag.shift) self.comb += self.cpu.jtag_update.eq(self.jtag.update) self.comb += self.cpu.jtag_reset.eq(self.jtag.reset) self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi) self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo)
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50", with_analyzer=False, **kwargs): platform = Platform() sys_clk_freq = int(1e9/platform.default_clk_period) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, ident="LiteX Simulation", ident_version=True, with_uart=False, **kwargs) # crg self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # serial self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # sdram if with_sdram: sdram_module = IS42S16160(sys_clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram( self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_refresh=False)) # reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) assert not (with_ethernet and with_etherbone) # FIXME: fix simulator with 2 ethernet interfaces # ethernet if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac) self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) # etherbone if with_etherbone: # eth phy self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME # eth core etherbonecore = LiteEthUDPIPCore(self.etherbonephy, etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq) if with_ethernet: etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore) self.submodules.etherbonecore = etherbonecore # etherbone self.submodules.etherbone = LiteEthEtherbone(self.etherbonecore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # analyzer if with_analyzer: analyzer_signals = [ # FIXME: find interesting signals to probe self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, sys_clk_freq=int(75e6), cpu_count=1, with_ethernet=False, **kwargs): VexRiscvSMP.litedram_width = 128 VexRiscvSMP.ibus_width = 64 VexRiscvSMP.dbus_width = 64 VexRiscvSMP.coherent_dma = True platform = trellisboard.Platform(toolchain="trellis") # SoCCore ---------------------------------------------------------------------------------- kwargs["integrated_rom_size"] = 0x10000 kwargs["csr_data_width"] = 8 SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_cls=VexRiscvSMP, cpu_variant="default", **kwargs) self.add_constant("config_cpu_count", cpu_count) # for dts generation # PLIC ------------------------------------------------------------------------------------ self.bus.add_slave("plic", self.cpu.plicbus, region=SoCRegion(origin=0xf0C00000, size=0x400000, cached=False)) # CLINT ------------------------------------------------------------------------------------ self.bus.add_slave("clint", self.cpu.cbus, region=SoCRegion(origin=0xf0010000, size=0x10000, cached=False)) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = ECP5DDRPHY(pads=PHYPadsReducer( platform.request("ddram"), [0, 1]), sys_clk_freq=sys_clk_freq) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41J256M16(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True, controller_settings=ControllerSettings( cmd_buffer_buffered=False, with_auto_precharge=False)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy)