def main(): with open("README.md") as f: description = [str(f.readline()) for i in range(7)] parser = argparse.ArgumentParser(description="".join(description[1:]), formatter_class=argparse.RawTextHelpFormatter) parser.add_argument("--build", action="store_true", help="build bitstream") parser.add_argument("--load", action="store_true", help="load bitstream (to SRAM)") parser.add_argument("--device", default="xc7a35t", help="FPGA device (xc7a35t (default) or xc7a100t)") args = parser.parse_args() if not args.build and not args.load: parser.print_help() if args.build: print("[build {}]...".format(args.device)) os.makedirs("build/gateware", exist_ok=True) os.system("cd usb3_core/daisho && make && ./usb_descrip_gen") os.system("cp usb3_core/daisho/usb3/*.init build/gateware/") platform = netv2.Platform(device=args.device) platform.add_extension(_usb3_io) soc = USB3SoC(platform) builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv") builder.build() if args.load: print("[load]...") load()
def main(): with open("README.md") as f: description = [str(f.readline()) for i in range(1, 9)] parser = argparse.ArgumentParser( description="".join(description[1:]), formatter_class=argparse.RawTextHelpFormatter) parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream") args = parser.parse_args() if args.load: from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd.cfg") prog.load_bitstream("build/gateware/top.bit") exit() if args.flash: from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd.cfg", flash_proxy_basename="openocd/bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") prog.flash(0, "build/gateware/top.bin") exit() platform = netv2.Platform() platform.add_extension(_pcie_analyzer_io) soc = PCIeAnalyzer(platform) builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv") builder.build(run=args.build)
def main(): with open("README") as f: description = [str(f.readline()) for i in range(7)] parser = argparse.ArgumentParser( description="".join(description[0:]), formatter_class=argparse.RawTextHelpFormatter) parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream") args = parser.parse_args() platform = netv2.Platform() soc = NeTV2(platform) builder = Builder(soc, csr_csv="test/csr.csv") builder.build(run=args.build) soc.generate_software_headers() if args.load: prog = soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if args.flash: prog = soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): platform = netv2.Platform() # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=integrated_rom_size, integrated_sram_size=0x8000, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = K4B2G1646F(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): platform = netv2.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=K4B2G1646F(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_spi_xip=False, **kwargs): platform = netv2.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=K4B2G1646F(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # SPI XIP ---------------------------------------------------------------------------------- if with_spi_xip: from litespi import LiteSPI from litespi.phy.generic import LiteSPIPHY spi_xip_size = 1024 * 1024 * 8 self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x")) self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness) spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None), size=spi_xip_size, cached=False) self.bus.add_slave(name="spixip", slave=self.spictl.bus, region=spi_xip_region) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy)
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): platform = netv2.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=integrated_rom_size, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform, sys_clk_freq) # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)