def do_finalize(self, fragment): # Add the CRG crg = CRG(self.request("clk50")) fragment += crg.get_fragment() clocks = { "clk50": 50.0, "clk12": 12.0, ("ulpi", "clk"): 60.0, ("ftdi", "clk"): 60.0 } # Make sure init_b is used / added to the UCF self.request("init_b") for name, mhz in clocks.items(): period = 1000.0 / mhz try: if isinstance(name, tuple): clk = getattr(self.lookup_request(name[0]), name[1]) else: clk = self.lookup_request(name) self.add_platform_command(""" NET "{clk}" TNM_NET = "GRP{clk}"; TIMESPEC "TS{clk}" = PERIOD "GRP{clk}" %f ns HIGH 50%%; """ % period, clk=clk) except ConstraintError: pass
def finalize(self, fragment, *args, **kwargs): if self.finalized: raise ConstraintError("Already finalized") # if none exists, create a default clock domain and drive it if not fragment.clock_domains: if not hasattr(self, "default_clk_name"): raise NotImplementedError( "No default clock and no clock domain defined") crg = CRG(self.request(self.default_clk_name)) fragment += crg.get_fragment() self.do_finalize(fragment, *args, **kwargs) self.finalized = True
def __init__(self, platform): sys_clk_freq = int(32e6) SC.SoCCore.__init__(self, platform, cpu_type="lm32", clk_freq=32e6, csr_data_width=32, ident="GameSnake", ident_version=True, integrated_rom_size=0x8000, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk32"), ~platform.request("cpu_reset")) #Button_interrupt button_in = Cat(*[platform.request("user_btn", i) for i in range(5)]) self.submodules.buttons = btnintrupt(button_in) #lcd parallel self.submodules.lcd_test = LCD_i80(sys_clk_freq) self.comb += [ platform.request("db").eq(self.lcd_test.db_), platform.request("cs").eq(self.lcd_test.cs_), platform.request("rs").eq(self.lcd_test.rs_), platform.request("rd").eq(self.lcd_test.rd_), platform.request("wr").eq(self.lcd_test.wr_), platform.request("rst").eq(self.lcd_test.rst_), ] # SD_spi self.submodules.spi_sd = SPIMaster(platform.request("SD")) self.comb += platform.request("uCD").eq(0x1)
def __init__(self, with_ethernet=False): platform = Platform() sys_clk_freq = int(1e6) SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, integrated_rom_size=0x8000, integrated_main_ram_size=0x02000000, # 32MB integrated_main_ram_init=get_mem_data( { "buildroot/Image": "0x00000000", "buildroot/rootfs.cpio": "0x00800000", "buildroot/rv32.dtb": "0x01000000" }, "little")) self.add_constant("SIM", None) # supervisor self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # crg self.submodules.crg = CRG(platform.request("sys_clk")) # machine mode emulator ram emulator_rom = get_mem_data("emulator/emulator.bin", "little") self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # serial self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) # ethernet if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac")
def __init__(self, platform): sys_clk_freq = int(100e6) # SoC with CPU SoCCore.__init__(self, platform, cpu_type="lm32", clk_freq=100e6, ident="CPU Test SoC", ident_version=True, integrated_rom_size=0x8000, csr_data_width=32, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset")) # Led user_leds = Cat(*[platform.request("user_led", i) for i in range(16)]) self.submodules.leds = Led(user_leds) # Buttons user_buttons = Cat( *[platform.request("user_btn", i) for i in range(5)]) self.submodules.buttons = Button(user_buttons) # lcd self.submodules.SD = SPIMaster(platform.request("sd_spi")) #sdcard # Display self.submodules.display = Display(sys_clk_freq) self.comb += [ platform.request("display_cs_n").eq(~self.display.cs), platform.request("display_abcdefg").eq(~self.display.abcdefg) ]
def __init__(self, platform): sys_clk_freq = int(100e6) # SoC with CPU SoCCore.__init__(self, platform, cpu_type="vexriscv", clk_freq=100e6, ident="LiteX CPU Test SoC", ident_version=True, integrated_rom_size=0x8000, integrated_main_ram_size=0x4000) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset")) # FPGA identification self.submodules.dna = dna.DNA() self.add_csr("dna") # FPGA Temperature/Voltage self.submodules.xadc = xadc.XADC() self.add_csr("xadc") # Led user_leds = Cat(*[platform.request("user_led", i) for i in range(16)]) self.submodules.leds = Led(user_leds) self.add_csr("leds") # Switches user_switches = Cat( *[platform.request("user_sw", i) for i in range(16)]) self.submodules.switches = Switch(user_switches) self.add_csr("switches") # Buttons user_buttons = Cat( *[platform.request("user_btn", i) for i in range(5)]) self.submodules.buttons = Button(user_buttons) self.add_csr("buttons") # RGB Led self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0)) self.add_csr("rgbled") # Accelerometer self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"), data_width=32, sys_clk_freq=sys_clk_freq, spi_clk_freq=1e6) self.add_csr("adxl362") # SevenSegmentDisplay self.submodules.display = SevenSegmentDisplay(sys_clk_freq) self.add_csr("display") self.comb += [ platform.request("display_cs_n").eq(~self.display.cs), platform.request("display_abcdefg").eq(~self.display.abcdefg) ]
def __init__(self, platform): sys_clk_freq = int(100e6) # SoC with CPU SoCCore.__init__(self, platform, cpu_type="lm32", clk_freq=100e6, ident="CPU Test SoC", ident_version=True, integrated_rom_size=0x8000, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset")) # FPGA identification self.submodules.dna = dna.DNA() # Buttons user_buttons = Cat( *[platform.request("user_btn", i) for i in range(5)]) self.submodules.buttons = Button(user_buttons) # lcd self.submodules.lcd = SPIMaster(platform.request("lcd_spi")) self.submodules.rs = Led(platform.request("rs_lcd")) self.submodules.rst = Led(platform.request("rst_lcd"))
def __init__(self, revision): platform = colorlight_5a_75e.Platform(revision) sys_clk_freq = int(25e6) platform.add_extension(_serial) platform.add_extension(_leds) # SoC with CPU SoCCore.__init__(self, platform, cpu_type="vexriscv", clk_freq=25e6, ident="LiteX CPU Test SoC 5A-75E", ident_version=True, integrated_rom_size=0x8000, integrated_main_ram_size=0x4000) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk25"), ~platform.request("user_btn_n")) # Led user_leds = Cat(*[platform.request("user_led", i) for i in range(2)]) self.submodules.leds = Led(user_leds) self.add_csr("leds")
def __init__(self, platform): sys_clk_freq = int(100e6) # SoC with CPU SoCCore.__init__(self, platform, cpu_type="lm32", clk_freq=100e6, ident="CPU Test SoC", ident_version=True, integrated_rom_size=0x8000, csr_data_width=32, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset")) # Led user_leds = Cat(*[platform.request("user_led", i) for i in range(16)]) self.submodules.leds = Led(user_leds) # Buttons user_buttons = Cat( *[platform.request("user_btn", i) for i in range(5)]) self.submodules.buttons = Button(user_buttons) # lcd self.submodules.spi_sd = SPIMaster(platform.request("SD")) self.comb += platform.request("uCD").eq(0x1)
def __init__(self, platform): sys_clk_freq = int(100e6) # SoC with CPU interrupt_map = { "botones": 4, } SoCCore.interrupt_map.update(interrupt_map) SoCCore.__init__(self, platform, cpu_type="lm32", clk_freq=100e6, ident="CPU Test SoC", ident_version=True, integrated_rom_size=0x8000, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset")) #botones con interrupcion bot = Cat(*[platform.request("boton", i) for i in range(8)]) self.submodules.botones = btnintrupt(bot) # lcd self.submodules.lcd = SPIMaster(platform.request("lcd_spi")) self.submodules.rs = Led(platform.request("rs_lcd")) self.submodules.rst = Led(platform.request("rst_lcd")) #Memoria SD self.submodules.SD = SPIMaster(platform.request("sd_spi"))
def __init__(self, platform): clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoC.__init__(self, platform, clk_freq, cpu_type="none", with_csr=True, csr_data_width=32, with_uart=False, with_identifier=True, with_timer=False) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq) self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False) # Wishbone Bridge usb_bridge_port = self.usb_core.crossbar.get_port( self.usb_map["bridge"]) self.add_cpu_or_bridge( LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq)) self.add_wb_master(self.cpu_or_bridge.wishbone) # Leds leds = Cat(iter([platform.request("user_led", i) for i in range(8)])) self.submodules.leds = GPIOOut(leds)
def __init__(self, revision): platform = colorlight_5a_75b.Platform(revision) sys_clk_freq = int(25e6) # custom serial using j1 pins instead of led & button platform.add_extension(_serialx) # SoC with CPU SoCCore.__init__(self, platform, cpu_type="vexriscv", clk_freq=25e6, ident="LiteX CPU Test SoC 5A-75B", ident_version=True, integrated_rom_size=0x8000, integrated_main_ram_size=0x4000, uart_name="serialJx") # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk25"), 0) # Led user_leds = Cat(*[platform.request("user_led_n", i) for i in range(1)]) self.submodules.leds = Led(user_leds) self.add_csr("leds")
def __init__(self, **kwargs): platform = sim.Platform() SoCSDRAM.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, ident="LiteX simulation example design", with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) if not self.integrated_main_ram_size: sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_refresh=False)) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
def __init__(self, platform, **kwargs): SoCCore.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, integrated_main_ram_size=16*1024, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name))
def __init__(self, platform): clk_freq = 100e6 self.submodules.crg = CRG(platform.request("clk100")) refclk = Signal() refclk_pads = platform.request("gtx_refclk") self.specials += [ Instance("IBUFDS_GTE2", i_CEB=0, i_I=refclk_pads.p, i_IB=refclk_pads.n, o_O=refclk) ] cpll = GTXChannelPLL(refclk, 125e6, 2.5e9) print(cpll) self.submodules += cpll tx_pads = platform.request("gtx_tx") rx_pads = platform.request("gtx_rx") gtx = GTX(cpll, tx_pads, rx_pads, clk_freq, clock_aligner=False) self.submodules += gtx counter = Signal(8) self.sync.tx += counter.eq(counter + 1) self.comb += [ gtx.encoder.k[0].eq(1), gtx.encoder.d[0].eq((5 << 5) | 28), gtx.encoder.k[1].eq(0), gtx.encoder.d[1].eq(counter), ]
def main(): platform = kc705.Platform() top = MicroscopeDemo(platform.request("serial"), 1e9 / platform.default_clk_period) clock = platform.request(platform.default_clk_name) top.submodules += CRG(clock) platform.build(top)
def __init__(self, platform): sys_clk_freq = int(32e6) # SoC with CPU SC.SoCCore.__init__(self, platform, cpu_type="lm32", clk_freq=32e6, csr_data_width=32, ident="CPU Test SoC", ident_version=True, integrated_rom_size=0x8000, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk32"), ~platform.request("cpu_reset")) self.submodules.led = Led(platform.request("led01", 0)) self.submodules.button = Button(platform.request("button01", 0)) # interrupts declaration interrupt_map = { "button": 4, } SC.SoCCore.interrupt_map.update(interrupt_map) print(SC.SoCCore.interrupt_map)
def __init__(self, platform, **kwargs): sys_clk_freq = int(1e9/platform.default_clk_period) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request(platform.default_clk_name))
def __init__(self): platform = nexys4ddr.Platform() # SoC with CPU SoCCore.__init__(self, platform, cpu_type="picorv32", clk_freq=100e6, integrated_rom_size=0x8000, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset")) # Leds SoCCore.add_csr(self, "leds") user_leds = Cat(*[platform.request("led", i) for i in range(16)]) self.submodules.leds = gpio.GPIOOut(user_leds) # Switchs SoCCore.add_csr(self, "switchs") user_switchs = Cat(*[platform.request("sw", i) for i in range(16)]) self.submodules.switchs = gpio.GPIOIn(user_switchs) # Buttons SoCCore.add_csr(self, "buttons") user_buttons = Cat( * [platform.request("btn%c" % c) for c in ['c', 'd', 'u', 'r', 'l']]) self.submodules.buttons = gpio.GPIOIn(user_buttons) # RGB leds SoCCore.add_csr(self, "led16") self.submodules.led16 = rgbled.RGBLed(platform.request("led", 16)) SoCCore.add_csr(self, "led17") self.submodules.led17 = rgbled.RGBLed(platform.request("led", 17)) # 7segments Display SoCCore.add_csr(self, "display") display_segments = Cat( *[platform.request("display_segment", i) for i in range(8)]) display_digits = Cat( *[platform.request("display_digit", i) for i in range(8)]) self.submodules.display = sevensegment.SevenSegment( display_segments, display_digits) # Joystick SPI SoCCore.add_csr(self, "joystick") self.submodules.joystick = spijoystick.SpiJoystick( platform.request("joystick")) # VGA SoCCore.add_csr(self, "vga_cntrl") vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)]) vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)]) vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)]) self.submodules.vga_cntrl = vgacontroller.VGAcontroller( platform.request("hsync"), platform.request("vsync"), vga_red, vga_green, vga_blue)
def __init__(self, **kwargs): # Setting sys_clk_freq too low will cause wishbone timeouts !!! sys_clk_freq = int(20e6) print(kwargs) SoCCore.__init__(self, SimPlatform("SIM", _io), clk_freq=sys_clk_freq, integrated_rom_size=0, integrated_sram_size=0, ident="LiteX Simulation", ident_version=True, with_uart=False, **kwargs) # crg self.submodules.crg = CRG(self.platform.request("sys_clk")) # ---------------------------- # Virtual serial to Wishbone bridge # ---------------------------- # bridge virtual serial phy as wishbone master self.submodules.uart_phy = RS232PHYModel( self.platform.request("serial")) self.submodules.uartbone = \ Stream2Wishbone(self.uart_phy, clk_freq=self.clk_freq) self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
def __init__(self, platform): sys_clk_freq = int(100e6) # SoC with CPU interrupt_map = { "buttoniner": 4, } SoCCore.interrupt_map.update(interrupt_map) SoCCore.__init__(self, platform, cpu_type="lm32", clk_freq=100e6, ident="CPU Test SoC", ident_version=True, integrated_rom_size=0x8000, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset")) # Led user_leds = Cat(*[platform.request("user_led", i) for i in range(8)]) self.submodules.leds = Led(user_leds) # Buttons interrupcion bten = Cat(*[platform.request("user_btn", i) for i in range(8)]) self.submodules.buttoniner = btnintrupt(bten)
def __init__(self, platform): sys_clk_freq = int(100e6) # SoC with CPU SC.SoCCore.__init__(self, platform, cpu_type="lm32", clk_freq=100e6, ident="CPU Test SoC", ident_version=True, integrated_rom_size=0x8000, csr_data_width=32, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk32"), ~platform.request("cpu_reset")) # Led user_leds = Cat(*[platform.request("user_led", i) for i in range(9)]) self.submodules.leds = Led(user_leds) # Spi self.submodules.spi = SPIMaster(platform.request("spi_master")) # control_lcd control_lcd = Cat( *[platform.request("control_lcd", i) for i in range(3)]) self.submodules.ctrllcd = gpio.GPIOOut(control_lcd) self.submodules.i2s = I2S(platform.request("i2s_"))
def __init__(self, platform, **kwargs): SoC.__init__(self, platform, clk_freq=100 * 1000000, integrated_rom_size=0x8000, **kwargs) self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n")) self.comb += platform.request("user_led", 0).eq(ResetSignal())
def __init__(self): platform = tarjeta.Platform() # SoC with CPU SoCCore.__init__( self, platform, cpu_type="picorv32", # cpu_type="vexriscv", clk_freq=100e6, integrated_rom_size=0x6000, integrated_main_ram_size=2 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk"), ~platform.request("cpu_reset")) # Leds SoCCore.add_csr(self, "leds") user_leds = Cat(*[platform.request("led", i) for i in range(10)]) self.submodules.leds = gpio.GPIOOut(user_leds) # Switchs SoCCore.add_csr(self, "switchs") user_switchs = Cat(*[platform.request("sw", i) for i in range(8)]) self.submodules.switchs = gpio.GPIOIn(user_switchs) # Buttons SoCCore.add_csr(self, "buttons") user_buttons = Cat( *[platform.request("btn%c" % c) for c in ['c', 'r', 'l']]) self.submodules.buttons = gpio.GPIOIn(user_buttons) # 7segments Display SoCCore.add_csr(self, "display") display_segments = Cat( *[platform.request("display_segment", i) for i in range(8)]) display_digits = Cat( *[platform.request("display_digit", i) for i in range(8)]) self.submodules.display = sevensegment.SevenSegment( display_segments, display_digits) # RGB leds SoCCore.add_csr(self, "ledRGB_1") self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1)) SoCCore.add_csr(self, "ledRGB_2") self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2)) # VGA SoCCore.add_csr(self, "vga_cntrl") vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)]) vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)]) vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)]) self.submodules.vga_cntrl = vgacontroller.VGAcontroller( platform.request("hsync"), platform.request("vsync"), vga_red, vga_green, vga_blue)
def __init__(self, platform): sys_clk_freq = int((1e9 / platform.default_clk_period)) SoCCore.__init__(self, platform, sys_clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="Litescope example design", ident_version=True, with_timer=False) # crg self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # bridge self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) # Litescope IO self.submodules.io = LiteScopeIO(8) for i in range(8): try: self.comb += platform.request("user_led", i).eq(self.io.output[i]) except: pass # Litescope Analyzer analyzer_groups = {} # counter group counter = Signal(16, name_override="counter") zero = Signal(name_override="zero") self.sync += counter.eq(counter + 1) self.comb += zero.eq(counter == 0) analyzer_groups[0] = [zero, counter] # communication group analyzer_groups[1] = [ platform.lookup_request("serial").tx, platform.lookup_request("serial").rx, self.cpu_or_bridge.wishbone ] # fsm group fsm = FSM(reset_state="STATE1") self.submodules += fsm fsm.act("STATE1", NextState("STATE2")) fsm.act("STATE2", NextState("STATE1")) analyzer_groups[2] = [fsm] # analyzer self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
def __init__(self, platform): sys_clk_freq = int(100e6) SoCCore.__init__( self, platform, cpu_type="lm32", clk_freq=100e6, ident="CPU Test SoC", ident_version=True, integrated_rom_size=0x8000, integrated_main_ram_size=16 * 1024, ) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset")) # FPGA identification self.submodules.dna = dna.DNA() # FPGA Temperature/Voltage self.submodules.xadc = xadc.XADC() # Led user_leds = Cat(*[platform.request("user_led", i) for i in range(16)]) self.submodules.leds = Led(user_leds) # Switches user_switches = Cat( *[platform.request("user_sw", i) for i in range(16)]) self.submodules.switches = Switch(user_switches) # Buttons user_buttons = Cat( *[platform.request("user_btn", i) for i in range(5)]) self.submodules.buttons = Button(user_buttons) # RGB Led self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0)) # Accelerometer self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi")) # Display self.submodules.display = Display(sys_clk_freq) self.comb += [ platform.request("display_cs_n").eq(~self.display.cs), platform.request("display_abcdefg").eq(~self.display.abcdefg) ] # SD self.submodules.SD = SD(platform.request("SD"), platform.request("butt"), "csr") # LCD self.submodules.LCD = SPIMaster(platform.request("LCD"))
def __init__(self, **kwargs): platform = Platform() sys_clk_freq = int(1e6) SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, integrated_rom_size=0xC000, integrated_main_ram_size=0x02000000, # 32MB **kwargs) # supervisor self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # crg self.submodules.crg = CRG(platform.request("sys_clk")) # machine mode emulator ram emulator_rom = get_mem_data("emulator/emulator.bin", "little") self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # serial self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) # Integrate Adder8 self.submodules.adder8 = Adder8() self.add_csr("adder8", 10, allow_user_defined=True) # Integrate CAN # self.submodules.can_ctrl = can_ctrl = SJA1000(platform.request("canif", 0)) # self.add_csr("can_ctrl", 11, allow_user_defined=True) # self.add_interrupt("can_ctrl", 6, allow_user_defined=True) # self.register_mem("can_ctrl", 0x30000000, can_ctrl.bus, 512) # can_ctrl.add_source(platform) # platform.add_verilog_include_path("periphs/verilog/can") # Integrate SPI master self.submodules.spi_master = spi_master = SpiMaster( self.platform.request("spi", 0)) self.add_csr("spi_master", 11, allow_user_defined=True) self.add_interrupt("spi_master", 6, allow_user_defined=True) self.register_mem("spi_master", 0x30000000, spi_master.bus, 32) spi_master.add_source(self.platform) platform.add_verilog_include_path("periphs/verilog/spi")
def __init__(self, platform, **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x10000) if kwargs.get('cpu_type', None) == 'mor1kx': dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) dict_set_max(kwargs, 'firmware_ram_size', 0x10000) if 'firmware_filename' not in kwargs: kwargs[ 'firmware_filename'] = "build/sim_{}_{}/software/firmware/firmware.fbi".format( self.__class__.__name__.lower()[:-3], kwargs.get('cpu_type', 'lm32')) clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM( firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.flash_boot_address = self.mem_map["firmware_ram"] define_flash_constants(self) # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings(memtype="SDR", dfi_databits=1 * 32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1)
def __init__(self, platform, integrated_rom_size=0x8000, **kwargs): sys_clk_freq = int(1e9 / platform.default_clk_period) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=integrated_rom_size, integrated_main_ram_size=16 * 1024, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request(platform.default_clk_name))
def __init__(self, platform, clk_freq=int(166e6), mac_address=0x10e2d5000000, ip_address="192.168.1.50"): sys_clk_freq = int((1 / (platform.default_clk_period)) * 1e9) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="LiteEth Base Design", with_timer=False) # Serial Wishbone Bridge serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200) self.submodules += serial_bridge self.add_wb_master(serial_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # Wishbone SRAM (to test Wishbone over UART and Etherbone) self.submodules.sram = wishbone.SRAM(1024) self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus) # Ethernet PHY and UDP/IP stack self.submodules.ethphy = ethphy = LiteEthPHY( clock_pads=platform.request("eth_clocks"), pads=platform.request("eth"), clk_freq=clk_freq) self.add_csr("ethphy") self.submodules.ethcore = ethcore = LiteEthUDPIPCore( phy=ethphy, mac_address=mac_address, ip_address=ip_address, clk_freq=clk_freq) self.add_csr("ethcore") if isinstance(platform.toolchain, XilinxVivadoToolchain): self.crg.cd_sys.clk.attr.add("keep") ethphy.crg.cd_eth_rx.clk.attr.add("keep") ethphy.crg.cd_eth_tx.clk.attr.add("keep") platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6) platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 125e6) platform.add_false_path_constraints(self.crg.cd_sys.clk, ethphy.crg.cd_eth_rx.clk, ethphy.crg.cd_eth_tx.clk)