def synthesize(opc): syn = Synthesizer() syn.addInput(BitVecVar('r0', 8)) syn.addInput(BitVecVar('r1', 8)) syn.addInput(BitVecVar('opcode', 2)) r0 = syn.inp('r0') r1 = syn.inp('r1') opcode = syn.inp('opcode') ra = Choice('ra', None, [r0, r1]) add_r = Add(r0, ra) sub_r = Sub(r0, ra) r0_next = Choice('r0_next', None, [add_r, sub_r]) syn.addOutput('r0', r0_next, Synthesizer.BITVEC) syn.debug(vb=2, lf=sys.stdout, uc=True) cnst = Equal(opcode, BitVecVal(opc, 2)) r = syn.synthesize(['r0'], [cnst], alu_sim) print str(r[0]) print '-' * 40
def eval(op, inputs, outputs): a = inputs['a'] b = inputs['b'] c = inputs['c'] if op == 0: outputs['r'] = ((a + b) & 0xFF) if c == 227 else 0 else: outputs['r'] = (a + op) & 0xFF syn = Synthesizer() a = syn.addInput(ast.BitVecVar('a', 8)) b = syn.addInput(ast.BitVecVar('b', 8)) c = syn.addInput(ast.BitVecVar('c', 8)) r_add = ast.If( ast.Equal(c, ast.BVInRange('c', ast.BitVecVal(220, 8), ast.BitVecVal(230, 8))), ast.Add(a, b), ast.BitVecVal(0, 8)) r_inc = ast.Add( a, ast.BVInRange('inc', ast.BitVecVal(1, 8), ast.BitVecVal(11, 8))) r = ast.Choice('r', None, [r_add, r_inc]) syn.addOutput('r', r, Synthesizer.BITVEC) syn.VERBOSITY = 2