Python-based Hardware Design Processing Toolkit for Verilog HDL Pyverilog is an open-source hardware design processing toolkit for Verilog HDL.

This software includes various tools for Verilog HDL design.

• vparser: Code parser to generate AST (Abstract Syntax Tree) from source codes of Verilog HDL.
• dataflow: Dataflow analyzer with an optimizer to remove redundant expressions and some dataflow handling tools.
• controlflow: Control-flow analyzer with condition analyzer that identify when a signal is activated.
• ast_code_generator: Verilog HDL code generator from AST(Abstract Syntax Tree).

You can create your own design analyzer, code translator and code generator of Verilog HDL based on this toolkit. For the complete tutorial, please follow the Wiki page.