rsYocto implements a modern Linux Kernel (linux-socfpga 5.5) and brings a set of today fundamentally needed components to Intel SoC-FPGAs and helps to simplify the complex process of development for FPGA-, Industrial 4.0-, Internet of things- or deep learning applications.

To realize that Python3 with the Python Package manager pip (PyPI) and the Apache Webserver with PHP are already included. Thereby it is really easy to install Python applications from the Raspberry Pi on a powerful Intel SoC-FPGA. rsYocto is for its best optimization complete console based, but the Apache Webserver can bring any GUI to Computers, Smartphones or Tablets, by hosting for example a monitor web interface. For that is the python Web framework Django 3.0 with the AdminLTE Dashboard pre-installed.

During development, a major concern was placed on the integration of powerful and simple to install development IDEs that do not require a JTAG-connection or any cross-building environment. All kinds of rsYocto applications and parts can build, deployed and even debugged over the network (fully rootable over the Internet). With the implementation of Microsoft Visual Studio and Visual Studio Code is a simple installment and quick jump start in the development process possible, because all required compilers run directly on rsYocto.

It is with the implementation of drivers for all Hard-IP Interfaces (e.g. I²C-, CAN-BUS,…) and simple Linux test commands (e.g. i2c-tools or can-utils) ready for the development of industrial connected solutions. With a single command rsYocto is capable to load a new FPGA configuration or to read and write the AXI-Bridge Interface to the FPGA fabric.

The “makersYoctoSDImage”- script allows developer to customize the rsYocto-image with the installment of their own applications, scripts or FPGA configuration files, that will be configured on the FPGA fabric before the Linux boots.

The final rsYocto-Image can be installed on a SD-Card with any commonly used Boot-Image creating tools. Versions are available for the Terasic DE10 Standard- (Cyclone V), Terasic DE10 Nano- (Cyclone V) and Terasic Han Pilot (Arria 10).

On the Terasic DE10 Nano board the Arduino Uno header can be used to connect external devices to a Hard-IP Bus, because the HPS interfaces with the pre-installed configuration are routed to FPGA I/O-Pins.

That was for me the starting point to try to develop my own fully optimized Linux distribution. Shortly after, I announced that the Intel development tools and documentations for HPS development are not nearly as good as those for the FPGA part. At the beginning it was really complicated to get anything running. After a hard time, I'm able to present this first working project. To get there, I designed my own built flow with my own scripts.

I think nearly everybody will have the same problems that I had during the development. For that reason, I try to give everybody a solution for their rapid prototyping. Within this repository I also integrated a step by step guide to show my solution with the Yocto project and the Intel EDS.

This project is by far not finished and issue free. I will continue my work and upload newer versions. I invite everybody to submit issues, comments and ideas.

Build, debug and deploy your applications over the network

Ready for powerful remote development IDEs and fitted with a Web server to host modern web applications

• Embedded Linux specially developed for Intel SoC-FPGAs
• Full usage of the Dual-Core ARM Cortex A9 with
  • the NEON-Engine
  • the vector floating point unit (VFP)
  • the Thumb-2 instruction set
• For the best performance completely custom optimized
• Console based (GUI less) with Busybox
• Watchdog timer is enabled

• FPGA fabric configuration during the boot and with a single Linux command
• Tools to interact with the FPGA fabric via the HPS to FPGA bridges
• Access the FPGA fabric with Shell scripts, C++-, Python-Applications or PHP or Django web applications
• HPS Hard IP components (I²C-,SPI-, CAN-BUS or UART) are routed to FPGA I/O
  • Ready for connecting different devices
    • e.g. Arduino Uno shields
• Console based Bus test tools (e.g. can-utils)

• Ethernet with dynamic and static iPv4 is supported
• SSH-Server starts automatically
• Support for remote based development IDEs pre-installed
  • Visual Studio Code for remote python debugging
  • Visual Studio for remote C++ debugging
    • gcc-compiler and gdb-server
• ARM DS-5 Streamline pre-installed and immediately after start ready for trace analysis

• Python3,Python3-dev
• Apache webserver with PHP and SQLite
• Latest Django version pre-installed for python-based web framework development
• The adminLTE web dashboard can bring modern complex web applications to SoC-FPGAs (example)

• git,curl and wget download manager
• Full integrated python pip package manager
• opkg package manager

• Building system to add the following to deployable and shareable images
  • Applications
  • Software Libraries
  • Web sites
  • Startup scripts
  • Info splash screen
  • Network Interface settings

• Full supported boards
  • Terasic DE10-Standard (Intel Cyclone V)
  • Terasic DE10-Nano (Intel Cyclone V)
  • Terasic HAN-Pilot (Intel Arria 10 SX)

The final rsYocto Versions are available inside the **release-Part of this repository**!

• Intel SoC FPGA Embedded Development Suite (EDS) 18.1.0.625 - Linux
• Intel Quartus Prime 18.1.0 Lite Edition - Cyclone V
• Intel Quartus Prime 18.1.0 Standard Edition - Arria 10
• The Yocto Project
• meta-intelfpga
• meta-openembedded
  • meta-python
  • meta-webserver
  • meta-networking
• meta-linaro
• meta-rstools

Required Build Flow to create rsYocto

This illustration shows my development procedure and the required complexity to create rsYocto. With this project I want to give other developers a full-functional system to reduce their development effort.

Also the rsyoctoMakingSDscript is recognizable, that on a running CentOS-Computer put all components, like the rootFs, bootloaders or own applications, together to create a bootable image file. This tool allows developer to do decent parts within a simple step, that was previously only possible with the Yocto project itself.

To show how to map FPGA I/O Pins with HPS Hard IP components, like I²C- or CAN-Bus, I wrote this step by step guide. Here also a description of the development of all necessary bootloaders and a bootloader script wih the Intel Embedded Development Suite (EDS) is available.

Inside my meta-intelfpga BSP layer I described in details how to get started with the Yocto project for Intel SoC-FPGAs.

Also I published a Yocto project meta layer (meta-rstools) to bring tools to update the FPGA configuration with the running Linux and to interact with simple commands with the FPGA fabric.

I designed a simple python script to pre-install Python pip (PyPI)- Packages within a final Yocto Project Linux Image (see here.

For the implementation of custom startup scripts to the boot process of an embedded Linux with Yocto project I added also a simple way to my meta-rstoolslayer.

This is shown within my "maping FPGA I/O Pins with HPS Hard IP components"-guide as well.

I will continue my work and upload newer versions. I invite everybody to submit issues, comments and ideas.

Currently I am working on a Windows 10 .net Desktop application to manage FPGA configurations and to allow to record data via the network. To release that I will design a server task, running on rsYocto, that can send python- or C++-values with TCP to the desktop. The following screenshot shows the development state of this project.

• Robin Sebastian

rsyocto and all my other projects I have fully developed by my own. No companies are involved in these projects. I’m recently graduated as a master in electrical engineering with the major embedded systems (M.Sc.).

I'm open for cooperations as a freelancer to realize your specific requirements. Otherwise, I‘m looking for an interesting full time job offer to share and deepen my shown skills.

Github sponsoring is welcome.