def _declr(self):
assert int(
self.DEPTH
) > 0, "FifoAsync is disabled in this case, do not use it entirely"
assert isPow2(
self.DEPTH), f"DEPTH has to be power of 2, is {self.DEPTH:d}"
# pow 2 because of gray conter counters
if self.EXPORT_SIZE or self.EXPORT_SPACE:
raise NotImplementedError()
self.dataIn_clk = Clk()
self.dataIn_clk.FREQ = self.IN_FREQ
self.dataOut_clk = Clk()
self.dataOut_clk.FREQ = self.OUT_FREQ
with self._paramsShared():
with self._associated(clk=self.dataIn_clk):
self.dataIn_rst_n = Rst_n()
with self._associated(rst=self.dataIn_rst_n):
self.dataIn = FifoWriter()
with self._associated(clk=self.dataOut_clk):
self.dataOut_rst_n = Rst_n()
with self._associated(rst=self.dataOut_rst_n):
self.dataOut = FifoReader()._m()
self.AW = log2ceil(self.DEPTH)
def _declr(self):
self.rx_clk = Clk(masterDir=DIRECTION.IN)
with self._associated(clk=self.rx_clk):
self.rx = GmiiRxChannel(masterDir=DIRECTION.IN)
self.tx_clk = Clk()
with self._associated(clk=self.tx_clk):
self.tx = GmiiTxChannel()
def _declr(self):
assert int(
self.DEPTH
) > 0, "FifoAsync is disabled in this case, do not use it entirely"
assert isPow2(self.DEPTH), "FifoAsync DEPTH has to be power of 2"
# pow 2 because of gray conter counters
if int(self.EXPORT_SIZE) or int(self.EXPORT_SPACE):
raise NotImplementedError()
self.dataIn_clk = Clk()
self.dataOut_clk = Clk()
self.rst_n = Rst_n()
with self._paramsShared():
with self._associated(clk=self.dataIn_clk):
self.dataIn = FifoWriter()
with self._associated(clk=self.dataOut_clk):
self.dataOut = FifoReader()._m()
self.pWr = GrayCntr()
self.pRd = GrayCntr()
self.addrW = log2ceil(self.DEPTH)
for cntr in [self.pWr, self.pRd]:
cntr.DATA_WIDTH.set(self.addrW)
def _declr(self):
assert isPow2(self.DEPTH - 1), (
"DEPTH has to be 2**n + 1"
" because fifo has have DEPTH 2**n"
" and 1 item is stored on output reg", self.DEPTH)
self.dataIn_clk = Clk()
self.dataOut_clk = Clk()
with self._paramsShared():
with self._associated(clk=self.dataIn_clk):
self.dataIn_rst_n = Rst_n()
with self._associated(rst=self.dataIn_rst_n):
self.dataIn = self.intfCls()
with self._associated(clk=self.dataOut_clk):
self.dataOut_rst_n = Rst_n()
with self._associated(rst=self.dataOut_rst_n):
self.dataOut = self.intfCls()._m()
f = self.fifo = FifoAsync()
f.IN_FREQ = self.IN_FREQ
f.OUT_FREQ = self.OUT_FREQ
DW = self.dataIn._bit_length() - 2 # 2 for control (valid, ready)
f.DATA_WIDTH = DW
# because the output register is used as another item storage
f.DEPTH = self.DEPTH - 1
f.EXPORT_SIZE = self.EXPORT_SIZE
f.EXPORT_SPACE = self.EXPORT_SPACE
SIZE_W = log2ceil(self.DEPTH + 1 + 1)
if self.EXPORT_SIZE:
self.size = VectSignal(SIZE_W, signed=False)
if self.EXPORT_SPACE:
self.space = VectSignal(SIZE_W, signed=False)
def _declr(self):
self.rst = Rst()
self.inData = Signal(dtype=self.DATA_TYP)
self.inClk = Clk()
self.outData = Signal(dtype=self.DATA_TYP)._m()
self.outClk = Clk()
def _declr(self):
self.clk = Clk()
with self._paramsShared():
self.io = TristateSig() # mosi and miso in one wire
self.cs = VectSignal(self.SLAVE_CNT) # chip select
self._associatedClk = self.clk
def _declr(self):
self.clk = Clk()
self.mosi = Signal() # master out slave in
self.miso = Signal(masterDir=DIRECTION.IN) # master in slave out
self.cs = VectSignal(self.SLAVE_CNT) # chip select
self._associatedClk = self.clk
def _declr(self):
with self._paramsShared():
def extData():
return VectSignal(self.DATA_WIDTH)
self.clk = Clk()
self.en = Signal()
self.we = Signal()
self.addr = VectSignal(self.ADDR_WIDTH)
self.in_w_a = extData()
self.in_w_b = extData()
self.in_r_a = extData()
self.in_r_b = extData()
self.out_w_a = extData()._m()
self.out_w_b = extData()._m()
self.out_r_a = extData()._m()
self.out_r_b = extData()._m()
with self._paramsShared():
r = self.bramR = RamMultiClock()
w = self.bramW = RamMultiClock()
r.PORT_CNT = w.PORT_CNT = 2
def _declr(self):
self.dataIn_clk = Clk()
self.dataIn_clk.FREQ = self.IN_FREQ
self.dataOut_clk = Clk()
self.dataOut_clk.FREQ = self.OUT_FREQ
with self._paramsShared():
with self._associated(clk=self.dataIn_clk):
self.dataIn_rst_n = Rst_n()
with self._associated(rst=self.dataIn_rst_n):
self.dataIn = AxiStreamFullDuplex()
with self._associated(clk=self.dataOut_clk):
self.dataOut_rst_n = Rst_n()
with self._associated(rst=self.dataOut_rst_n):
self.dataOut = AxiStreamFullDuplex()._m()
def _declr(self):
self.clk = Clk()
self.a = Signal()._m()
self.b = Signal()._m()
self.c = Signal()
self.d = Signal()
def _declr(self):
self.ref_clk = Clk(masterDir=self.CLK_MASTER_DIR)
self.ref_clk.FREQ = self.FREQ
with self._paramsShared():
with self._associated(clk=self.ref_clk):
self.tx = RmiiTxChannel()
self.rx = RmiiRxChannel(masterDir=DIRECTION.IN)
def _declr(self):
assert self.OUT_REG_CNT >= 2, self.OUT_REG_CNT
self.dataIn_clk = Clk()
self.dataIn_clk.FREQ = self.IN_FREQ
with self._associated(clk=self.dataIn_clk):
self.dataIn_rst = Rst()
with self._associated(rst=self.dataIn_rst):
self.dataIn = Signal(dtype=Bits(self.DATA_WIDTH))
self.dataOut_clk = Clk()
self.dataOut_clk.FREQ = self.OUT_FREQ
with self._associated(clk=self.dataOut_clk):
self.dataOut_rst = Rst()
with self._associated(rst=self.dataOut_rst):
self.dataOut = Signal(dtype=Bits(self.DATA_WIDTH))._m()
def _declr(self):
self.clk = Clk()
self.rst = Rst()
with self._associated(clk=self.clk, rst=self.rst):
self.data = TristateSig()
self.dir = Signal()
self.stop = Signal(masterDir=DIRECTION.IN)
self.next = Signal()
def _declr(self):
I_CLS = self.intfCls
self.dataIn_clk = Clk()
self.dataIn_clk.FREQ = self.IN_FREQ
with self._associated(self.dataIn_clk):
self.dataIn_rst_n = Rst_n()
self.dataOut_clk = Clk()
self.dataOut_clk.FREQ = self.OUT_FREQ
with self._associated(self.dataOut_clk):
self.dataOut_rst_n = Rst_n()
with self._paramsShared():
with self._associated(self.dataIn_clk, self.dataIn_rst_n):
self.dataIn = I_CLS()
with self._associated(self.dataOut_clk, self.dataOut_rst_n):
self.dataOut = I_CLS()._m()
def _declr(self):
PORTS = int(self.PORT_CNT)
self.clk = Clk()
with self._paramsShared():
# to let IDEs resolve type of port
self.a = BramPort_withoutClk()
for i in range(PORTS - 1):
self._sportPort(i + 1)
def _declr(self):
self.dataIn_clk = Clk()
self.dataOut_clk = Clk()
self.rst_n = Rst_n()
with self._paramsShared():
with self._associated(self.dataIn_clk):
self.dataIn = self.intfCls()
with self._associated(self.dataOut_clk):
self.dataOut = self.intfCls()._m()
f = self.fifo = FifoAsync()
DW = self.dataIn._bit_length() - 2 # 2 for control (valid, ready)
f.DATA_WIDTH.set(DW)
f.DEPTH.set(self.DEPTH - 1) # because there is an extra register
f.EXPORT_SIZE.set(self.EXPORT_SIZE)
if self.EXPORT_SIZE:
self.size = VectSignal(log2ceil(self.DEPTH + 1 + 1), signed=False)
def _declr(self):
self.a0 = Signal()
self.a1 = Signal()
self.a2 = Signal()
self.a3 = Signal()
self.a4 = Signal()
self.a5 = Signal()
self.d = Signal() # in
self.wclk = Clk()
self.o = Signal()._m() # out
self.we = Signal()
def _declr(self):
self.clk = Clk()
self.clk.FREQ = self.FREQ
assert self.HAS_MOSI or self.HAS_MISO
if self.HAS_MOSI:
self.mosi = Signal() # master out slave in
if self.HAS_MISO:
self.miso = Signal(masterDir=DIRECTION.IN) # master in slave out
if self.SLAVE_CNT is not None:
self.cs = VectSignal(self.SLAVE_CNT) # chip select
self._associatedClk = self.clk
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.s = Axi4Lite()
self.din0 = Handshaked()
self.dout0 = Handshaked()._m()
self.reg = HandshakedReg(Handshaked)
self.din1 = Handshaked()
self.dout1 = Handshaked()._m()
self.other_clk = Clk()
self.other_clk.FREQ = self.clk.FREQ * 2
with self._associated(clk=self.other_clk):
self.other_rst_n = Rst_n()
self.din2 = Handshaked()
self.dout2 = Handshaked()._m()
def _setup_clk_rst_n(self):
self.clk.FREQ = self.M_FREQ
self.rst_n._make_association(clk=self.clk)
self.s._make_association(clk=self.clk, rst=self.rst_n)
self.m_clk = Clk()
self.m_clk.FREQ = self.S_FREQ
self.m_rst_n = Rst_n()
self.m_rst_n._make_association(clk=self.m_clk)
self.m._make_association(clk=self.m_clk, rst=self.m_rst_n)
assert self.ADDR_BUFF_DEPTH == 1 or isPow2(self.ADDR_BUFF_DEPTH - 1), (
self.ADDR_BUFF_DEPTH, "size 2**n + 1 for output reg")
assert self.DATA_BUFF_DEPTH == 1 or isPow2(self.DATA_BUFF_DEPTH - 1), (
self.DATA_BUFF_DEPTH, "size 2**n + 1 for output reg")
def _declr(self):
PORT_CNT = self.PORT_CNT
with self._paramsShared():
self.clk = Clk()
# to let IDEs resolve type of port
self.firstA = BramPort_withoutClk()
self.secondA = BramPort_withoutClk()
if PORT_CNT == 2:
self.firstB = BramPort_withoutClk()
self.secondB = BramPort_withoutClk()
elif PORT_CNT > 2:
raise NotImplementedError()
self.select_sig = Signal()
self.ram0 = RamSingleClock()
self.ram1 = RamSingleClock()
def _declr(self):
super()._declr()
self.clk = Clk()
def _declr(self):
self.CLK = Clk()
# inputs
self.A = Signal(Bits(30))
self.B = Signal(Bits(18))
self.C = Signal(Bits(48))
self.D = Signal(Bits(25))
# selects the operands for main ALU
# [2:0] X
# [4:2] Y
# [7:4] Z
self.OPMODE = Signal(Bits(7))
# :ivar ALUMODE: selects the operation performed by main ALU
self.ALUMODE = Signal(Bits(4))
self.CECARRYIN = Signal()
self.CARRYINSEL = Signal(Bits(3))
# :ivar INMODE: Select the functionality of the pre-adder, the A,
# B, and D inputs, and the input registers. These bits should default to
# 5’b00000 if left unconnected. These are optionally invertible,
# providing routing flexibility.
self.INMODE = Signal(Bits(5))
self.CARRYIN = Signal()
# main outputs
self.OVERFLOW = Signal()._m()
self.P = Signal(Bits(48))._m()
self.PATTERNBDETECT = Signal()._m()
self.PATTERNDETECT = Signal()._m()
self.UNDERFLOW = Signal()._m()
self.CARRYOUT = Signal(Bits(4))._m()
# clock enable for internal registers
self.CEA1 = Signal()
self.CEA2 = Signal()
self.CEAD = Signal()
self.CEB1 = Signal()
self.CEB2 = Signal()
self.CEC = Signal()
self.CED = Signal()
self.CEM = Signal()
self.CEP = Signal()
self.CEALUMODE = Signal()
self.CECTRL = Signal()
self.CEINMODE = Signal()
# reset for internal registers
self.RSTA = Signal()
self.RSTALLCARRYIN = Signal()
self.RSTALUMODE = Signal()
self.RSTB = Signal()
self.RSTC = Signal()
self.RSTCTRL = Signal()
self.RSTD = Signal()
self.RSTINMODE = Signal()
self.RSTM = Signal()
self.RSTP = Signal()
# Column ports are used to connect the DSP blocks in the column
# and they have an equivalent port for fabric (e.g. A and ACIN).
self.ACIN = Signal(Bits(30))
self.ACOUT = Signal(Bits(30))._m()
self.BCIN = Signal(Bits(18))
self.BCOUT = Signal(Bits(18))._m()
# cary in/out for main ALU
self.CARRYCASCIN = Signal()
self.CARRYCASCOUT = Signal()._m()
self.PCIN = Signal(Bits(48))
self.PCOUT = Signal(Bits(48))._m()
# Sign of the multiplied result from the previous DSP48E1 slice for MACC extension.
self.MULTSIGNIN = Signal()
self.MULTSIGNOUT = Signal()._m()
self.input_check()
def _declr(self):
self.clk = Clk()
self.a = VectSignal(2)
self.b = VectSignal(2)
self.c = Signal()._m()
def _declr(self):
self.clk = Clk()
self._declr_ports()
self._declr_children()
def addClkRstn(obj):
"""
Construct clk, rst_n signal on object (usually Unit/Interface instance)
"""
obj.clk = Clk()
obj.rst_n = Rst_n()
def _declr(self):
self.clk = Clk()
self.clk.FREQ = self.FREQ
self._make_association(clk=self.clk)
self.d = VectSignal(self.DATA_WIDTH)
self.c = VectSignal(self.DATA_WIDTH // 8)
def _declr(self):
self.clk = Clk()
self.clk.FREQ = self.FREQ
with self._associated(clk=self.clk):
self.d = VectSignal(4)
self.ctl = Signal()
def _declr(self):
self.c = Clk()
self.c.FREQ = self.FREQ
with self._associated(clk=self.c):
self.io = TristateSig()
def _declr(self):
addClkRstn(self)
self.clkOut = Clk()._m()