def test_nested_struct_packed_array_index(do_test):
@bitstruct
class C:
bar: Bits16
@bitstruct
class B:
foo: Bits32
bar: [C] * 5
class A(Component):
def construct(s):
s.struct = InPort(B)
s.out = OutPort(C)
connect(s.struct.bar[1], s.out)
a = A()
a._ref_name = "A"
a._ref_ports = \
"""\
port_decls:
port_decl: out Port of Struct C
port_decl: struct Port of Struct B
"""
a._ref_wires = "wire_decls:\n"
a._ref_consts = "const_decls:\n"
a._ref_conns = \
"""\
connections:
connection: PackedIndex StructAttr CurCompAttr struct bar 1 -> CurCompAttr out
"""
a._ref_structs = [(rdt.Struct(
'B', {
'foo': rdt.Vector(32),
'bar': rdt.PackedArray([5], rdt.Struct('C',
{'bar': rdt.Vector(16)}))
}), 'B'), (rdt.Struct('C', {'bar': rdt.Vector(16)}), 'C')]
a._ref_src = \
"""\
struct C
struct B
component A
(
port_decls:
port_decl: out Port of Struct C
port_decl: struct Port of Struct B
interface_decls:
);
const_decls:
freevars:
wire_decls:
component_decls:
tmpvars:
upblk_srcs:
connections:
connection: PackedIndex StructAttr CurCompAttr struct bar 1 -> CurCompAttr out
endcomponent
"""
do_test(a)
def test_packed_array_port_array(do_test):
@bitstruct
class struct:
bar: Bits32
foo: [[Bits32] * 2] * 3
class A(Component):
def construct(s):
s.in_ = [InPort(struct) for _ in range(2)]
a = A()
foo = rdt.PackedArray([3, 2], rdt.Vector(32))
st = rdt.Struct('struct', {'bar': rdt.Vector(32), 'foo': foo})
a._ref_ports = [('clk', rt.Port('input', rdt.Vector(1))),
('in_', rt.Array([2], rt.Port('input', st))),
('reset', rt.Port('input', rdt.Vector(1)))]
a._ref_ports_yosys = [
('clk', rt.Port('input', rdt.Vector(1))),
('in___0__bar', rt.Port('input', rdt.Vector(32))),
('in___0__foo__0__0', rt.Port('input', rdt.Vector(32))),
('in___0__foo__0__1', rt.Port('input', rdt.Vector(32))),
('in___0__foo__1__0', rt.Port('input', rdt.Vector(32))),
('in___0__foo__1__1', rt.Port('input', rdt.Vector(32))),
('in___0__foo__2__0', rt.Port('input', rdt.Vector(32))),
('in___0__foo__2__1', rt.Port('input', rdt.Vector(32))),
('in___1__bar', rt.Port('input', rdt.Vector(32))),
('in___1__foo__0__0', rt.Port('input', rdt.Vector(32))),
('in___1__foo__0__1', rt.Port('input', rdt.Vector(32))),
('in___1__foo__1__0', rt.Port('input', rdt.Vector(32))),
('in___1__foo__1__1', rt.Port('input', rdt.Vector(32))),
('in___1__foo__2__0', rt.Port('input', rdt.Vector(32))),
('in___1__foo__2__1', rt.Port('input', rdt.Vector(32))),
('reset', rt.Port('input', rdt.Vector(1)))
]
do_test(a)
def test_nested_struct_packed_array_port_decl(do_test):
class C(BitStruct):
def __init__(s, bar=42):
s.bar = Bits16(bar)
class B(BitStruct):
def __init__(s, foo=0, bar=42):
s.foo = Bits32(foo)
s.bar = [C() for _ in range(5)]
class A(Component):
def construct(s):
s.struct = InPort(B)
a = A()
a._ref_name = "A"
a._ref_ports = \
"""\
port_decls:
port_decl: struct Port of Struct B
"""
a._ref_wires = "wire_decls:\n"
a._ref_consts = "const_decls:\n"
a._ref_conns = "connections:\n"
a._ref_structs = [(rdt.Struct(
'B', {
'foo':
rdt.Vector(32),
'bar':
rdt.PackedArray([5],
rdt.Struct('C', {'bar': rdt.Vector(16)}, ['bar']))
}, ['bar', 'foo']), 'B'),
(rdt.Struct('C', {'bar': rdt.Vector(16)}, ['bar']), 'C')]
a._ref_src = \
"""\
struct C
struct B
component A
(
port_decls:
port_decl: struct Port of Struct B
interface_decls:
);
const_decls:
freevars:
wire_decls:
component_decls:
tmpvars:
upblk_srcs:
connections:
endcomponent
"""
do_test(a)
def test_struct_packed_array_port_decl(do_test):
@bitstruct
class B:
foo: [Bits32] * 5
bar: Bits16
class A(Component):
def construct(s):
s.struct = InPort(B)
a = A()
a._ref_name = "A"
a._ref_ports = \
"""\
port_decls:
port_decl: struct Port of Struct B
"""
a._ref_wires = "wire_decls:\n"
a._ref_consts = "const_decls:\n"
a._ref_conns = "connections:\n"
a._ref_structs = [
(rdt.Struct('B', {
'foo': rdt.PackedArray([5], rdt.Vector(32)),
'bar': rdt.Vector(16)
}), 'B')
]
a._ref_src = \
"""\
struct B
component A
(
port_decls:
port_decl: struct Port of Struct B
interface_decls:
);
const_decls:
freevars:
wire_decls:
component_decls:
tmpvars:
upblk_srcs:
connections:
endcomponent
"""
do_test(a)
def test_packed_array_port_array(do_test):
class struct(BitStruct):
def __init__(s, bar=1, foo=42):
s.bar = Bits32(bar)
s.foo = [[Bits32(foo) for _ in range(2)] for _ in range(3)]
class A(Component):
def construct(s):
s.in_ = [InPort(struct) for _ in range(2)]
a = A()
foo = rdt.PackedArray([3, 2], rdt.Vector(32))
st = rdt.Struct('struct', {
'bar': rdt.Vector(32),
'foo': foo
}, ['bar', 'foo'])
a._ref_ports = [('clk', rt.Port('input', rdt.Vector(1))),
('in_', rt.Array([2], rt.Port('input', st))),
('reset', rt.Port('input', rdt.Vector(1)))]
a._ref_ports_yosys = [
('clk', rt.Port('input', rdt.Vector(1))),
('in___0__bar', rt.Port('input', rdt.Vector(32))),
('in___0__foo__0__0', rt.Port('input', rdt.Vector(32))),
('in___0__foo__0__1', rt.Port('input', rdt.Vector(32))),
('in___0__foo__1__0', rt.Port('input', rdt.Vector(32))),
('in___0__foo__1__1', rt.Port('input', rdt.Vector(32))),
('in___0__foo__2__0', rt.Port('input', rdt.Vector(32))),
('in___0__foo__2__1', rt.Port('input', rdt.Vector(32))),
('in___1__bar', rt.Port('input', rdt.Vector(32))),
('in___1__foo__0__0', rt.Port('input', rdt.Vector(32))),
('in___1__foo__0__1', rt.Port('input', rdt.Vector(32))),
('in___1__foo__1__0', rt.Port('input', rdt.Vector(32))),
('in___1__foo__1__1', rt.Port('input', rdt.Vector(32))),
('in___1__foo__2__0', rt.Port('input', rdt.Vector(32))),
('in___1__foo__2__1', rt.Port('input', rdt.Vector(32))),
('reset', rt.Port('input', rdt.Vector(1)))
]
do_test(a)
interface_decls:
);
const_decls:
freevars:
wire_decls:
component_decls:
tmpvars:
upblk_srcs:
connections:
connection: PackedIndex StructAttr CurCompAttr in_ foo 1 -> CurCompAttr out
endcomponent
''',
'REF_STRUCT',
[
(rdt.Struct('Bits32x5Foo', {'foo':rdt.PackedArray([5], rdt.Vector(32))}), 'Bits32x5Foo__foo_32x5'),
(rdt.Struct('NestedStructPackedArray', {'foo':rdt.PackedArray([5], rdt.Struct('Bits32x5Foo', {'foo':rdt.PackedArray([5], rdt.Vector(32))}))}), 'NestedStructPackedArray__foo_Bits32x5Foo__foo_32x5x5'),
]
)
CaseConnectValRdyIfcComp = set_attributes( CaseConnectValRdyIfcComp,
'REF_NAME',
'DUT',
'REF_IFC',
'''\
interface_decls:
interface_decl: in_ InterfaceView Bits32InValRdyIfc
interface_ports:
interface_port: msg Port of Vector32
interface_port: rdy Port of Vector1
interface_port: val Port of Vector1
interface_decls:
);
const_decls:
freevars:
wire_decls:
component_decls:
tmpvars:
upblk_srcs:
connections:
connection: PackedIndex StructAttr CurCompAttr in_ foo 1 -> CurCompAttr out
endcomponent
''', 'REF_STRUCT', [
(rdt.Struct(
'Bits32x5Foo',
{'foo': rdt.PackedArray([5], rdt.Vector(32))}), 'Bits32x5Foo'),
(rdt.Struct(
'NestedStructPackedArray', {
'foo':
rdt.Struct('Bits32x5Foo',
{'foo': rdt.PackedArray([5], rdt.Vector(32))})
}), 'NestedStructPackedArray'),
])
CaseConnectValRdyIfcComp = set_attributes(
CaseConnectValRdyIfcComp,
'REF_NAME',
'DUT',
'REF_IFC',
'''\
interface_decls:
def test_struct_packed_array(do_test):
class C(BitStruct):
def __init__(s, bar=1):
s.bar = Bits32(bar)
class B(BitStruct):
def __init__(s):
s.c = [C() for _ in range(2)]
class A(Component):
def construct(s):
s.in_ = InPort(B)
s.out = [OutPort(Bits32) for _ in range(2)]
connect(s.out[0], s.in_.c[0].bar)
connect(s.out[1], s.in_.c[1].bar)
a = A()
_C = rdt.Struct('C', {'bar': rdt.Vector(32)}, ['bar'])
a._ref_structs = [
( _C, \
"""\
typedef struct packed {
logic [31:0] bar;
} C;
""" ),
( rdt.Struct( 'B', {'c':rdt.PackedArray([2], _C)}, ['c'] ), \
"""\
typedef struct packed {
C [1:0] c;
} B;
""" ) ]
a._ref_ports = { a : \
"""\
input logic [0:0] clk,
input B in_,
output logic [31:0] out [0:1],
input logic [0:0] reset\
""" }
a._ref_wires = {a: ""}
a._ref_conns = { a : \
"""\
assign out[0] = in_.c[0].bar;
assign out[1] = in_.c[1].bar;\
""" }
# Yosys backend test reference output
a._ref_ports_port_yosys = { a : \
"""\
input logic [0:0] clk,
input logic [31:0] in___c__0__bar,
input logic [31:0] in___c__1__bar,
output logic [31:0] out__0,
output logic [31:0] out__1,
input logic [0:0] reset\
""" }
a._ref_ports_wire_yosys = { a : \
"""\
logic [31:0] in___c__bar [0:1];
logic [31:0] in___c [0:1];
logic [63:0] in_;
logic [31:0] out [0:1];\
""" }
a._ref_ports_conn_yosys = { a : \
"""\
assign in___c__bar[0] = in___c__0__bar;
assign in___c[0][31:0] = in___c__0__bar;
assign in___c__bar[1] = in___c__1__bar;
assign in___c[1][31:0] = in___c__1__bar;
assign in_[63:32] = in___c__1__bar;
assign in_[31:0] = in___c__0__bar;
assign out__0 = out[0];
assign out__1 = out[1];\
""" }
a._ref_wires_yosys = a._ref_wires
a._ref_conns_yosys = { a : \
"""\
assign out[0] = in___c__bar[0];
assign out[1] = in___c__bar[1];\
""" }
# TestVectorSimulator properties
def tv_in(m, tv):
m.in_ = tv[0]
def tv_out(m, tv):
assert m.out[0] == Bits32(tv[1])
assert m.out[1] == Bits32(tv[2])
a._test_vectors = [
[B(), 1, 1],
]
a._tv_in, a._tv_out = tv_in, tv_out
do_test(a)
def test_packed_array(do_test):
class B(BitStruct):
def __init__(s, foo=42):
s.foo = [Bits32(foo) for _ in range(2)]
class A(Component):
def construct(s):
s.in_ = InPort(B)
s.out = [OutPort(Bits32) for _ in range(2)]
connect(s.out[0], s.in_.foo[0])
connect(s.out[1], s.in_.foo[1])
a = A()
_foo = rdt.PackedArray([2], rdt.Vector(32))
a._ref_structs = [
( rdt.Struct( 'B', {'foo':_foo}, ['foo'] ), \
"""\
typedef struct packed {
logic [1:0][31:0] foo;
} B;
""" ) ]
a._ref_ports = { a : \
"""\
input logic [0:0] clk,
input B in_,
output logic [31:0] out [0:1],
input logic [0:0] reset\
""" }
a._ref_wires = {a: ""}
a._ref_conns = { a : \
"""\
assign out[0] = in_.foo[0];
assign out[1] = in_.foo[1];\
""" }
# Yosys backend test reference output
a._ref_ports_port_yosys = { a : \
"""\
input logic [0:0] clk,
input logic [31:0] in___foo__0,
input logic [31:0] in___foo__1,
output logic [31:0] out__0,
output logic [31:0] out__1,
input logic [0:0] reset\
""" }
a._ref_ports_wire_yosys = { a : \
"""\
logic [31:0] in___foo [0:1];
logic [63:0] in_;
logic [31:0] out [0:1];\
""" }
a._ref_ports_conn_yosys = { a : \
"""\
assign in___foo[0] = in___foo__0;
assign in___foo[1] = in___foo__1;
assign in_[63:32] = in___foo__1;
assign in_[31:0] = in___foo__0;
assign out__0 = out[0];
assign out__1 = out[1];\
""" }
a._ref_wires_yosys = a._ref_wires
a._ref_conns_yosys = { a : \
"""\
assign out[0] = in___foo[0];
assign out[1] = in___foo[1];\
""" }
# TestVectorSimulator properties
def tv_in(m, tv):
m.in_ = tv[0]
def tv_out(m, tv):
assert m.out[0] == Bits32(tv[1])
assert m.out[1] == Bits32(tv[2])
a._test_vectors = [
[B(), 42, 42],
[B(1), 1, 1],
[B(-1), -1, -1],
[B(-2), -2, -2],
[B(24), 24, 24],
]
a._tv_in, a._tv_out = tv_in, tv_out
do_test(a)
port_decl: in_ Port of Struct NestedStructPackedArray__foo_Bits32x5Foo__foo_32x5x5
port_decl: out Port of Struct Bits32x5Foo__foo_32x5
interface_decls:
);
const_decls:
freevars:
wire_decls:
component_decls:
tmpvars:
upblk_srcs:
connections:
connection: PackedIndex StructAttr CurCompAttr in_ foo 1 -> CurCompAttr out
endcomponent
''', 'REF_STRUCT', [
(rdt.Struct(Bits32x5Foo, {'foo': rdt.PackedArray([5], rdt.Vector(32))
}), 'Bits32x5Foo__foo_32x5'),
(rdt.Struct(
NestedStructPackedArray, {
'foo':
rdt.PackedArray(
[5],
rdt.Struct(Bits32x5Foo,
{'foo': rdt.PackedArray([5], rdt.Vector(32))}))
}), 'NestedStructPackedArray__foo_Bits32x5Foo__foo_32x5x5'),
])
CaseConnectValRdyIfcComp = set_attributes(
CaseConnectValRdyIfcComp,
'REF_NAME',
'DUT',