Exemplo n.º 1
0
 def _load_xilinx_device(self):
     device_name = self._cfg_manager.get_value("weblab_xilinx_experiment_xilinx_device")
     devices = [i for i in XilinxDevices.getXilinxDeviceValues() if i == device_name]
     if len(devices) == 1:
         return device_name, devices[0], XilinxImpact.create(devices[0], self._cfg_manager)
     else:
         raise UdXilinxExperimentErrors.InvalidXilinxDeviceError(device_name)
Exemplo n.º 2
0
 def _load_xilinx_device(self):
     self.device_name = self._cfg_manager.get_value('weblab_xilinx_experiment_xilinx_device')
     devices = [ i for i in XilinxDevices.getXilinxDeviceValues() if i == self.device_name ]
     if len(devices) == 1:
         return devices[0], XilinxImpact.create(devices[0], self._cfg_manager)
     else:
         raise UdXilinxExperimentErrors.InvalidXilinxDeviceError(self.device_name)
Exemplo n.º 3
0
        print "File received"
        content = base64.decodestring(serialized_content)

        fd, file_name = tempfile.mkstemp(prefix='weblab_fpga_program',
                                         suffix='.bit')
        try:
            os.write(fd, content)
            os.close(fd)

            print "Programming... %s" % file_name
            impact.program_device(file_name)

            print "Programmed successfully"
            return "ok"
        except:
            traceback.print_exc()
            raise
        finally:
            os.remove(file_name)


if __name__ == '__main__':
    cfg_manager = CM.ConfigurationManager()
    cfg_manager.append_path("config.py")
    impact = XilinxImpact.create(XilinxDevices.FPGA, cfg_manager)

    server = SimpleXMLRPCServer.SimpleXMLRPCServer(
        ('', cfg_manager.get_value("port")))
    server.register_instance(FpgaProgrammer())
    server.serve_forever()
Exemplo n.º 4
0
class FpgaProgrammer(object):
    def program(self, serialized_content):
        print "File received"
        content = base64.decodestring(serialized_content)

        fd, file_name = tempfile.mkstemp(prefix='weblab_fpga_program', suffix='.bit')
        try:
            os.write(fd, content)
            os.close(fd)

            print "Programming... %s" % file_name
            impact.program_device(file_name)

            print "Programmed successfully"
            return "ok"
        except:
            traceback.print_exc()
            raise
        finally:
            os.remove(file_name)

if __name__ == '__main__':
    cfg_manager = CM.ConfigurationManager()
    cfg_manager.append_path("config.py")
    impact = XilinxImpact.create(XilinxDevices.FPGA, cfg_manager)

    server = SimpleXMLRPCServer.SimpleXMLRPCServer(('', cfg_manager.get_value("port")))
    server.register_instance(FpgaProgrammer())
    server.serve_forever()