GitHub - babooppa6/Simulator: This is a simulator of a cache + memory hierarchy. It has a trace-driven input interface. The trace files are not included in the project.

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This is a simulator of a cache + memory hierarchy. It has a trace-driven input interface. The trace files are not included in the project.

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Name		Name	Last commit message	Last commit date
Latest commit History 58 Commits
Components		Components
Configs		Configs
Definitions		Definitions
Scripts		Scripts
Workloads		Workloads
analysis		analysis
bin		bin
results/1-core/baseline/lru/1m/astar		results/1-core/baseline/lru/1m/astar
.CmpXample.h		.CmpXample.h
.TableXample.h		.TableXample.h
.Template.h		.Template.h
.cproject		.cproject
.project		.project
BloomFilter.h		BloomFilter.h
CmpARC.h		CmpARC.h
CmpCache.h		CmpCache.h
CmpDCP.h		CmpDCP.h
CmpDRAMSim.h		CmpDRAMSim.h
CmpDynamicLLC.h		CmpDynamicLLC.h
CmpFDP.h		CmpFDP.h
CmpFDPAP.h		CmpFDPAP.h
CmpGenericLLC.h		CmpGenericLLC.h
CmpLLC.h		CmpLLC.h
CmpLLCDBI-old.h		CmpLLCDBI-old.h
CmpLLCDBI.h		CmpLLCDBI.h
CmpLLCVTS.h		CmpLLCVTS.h
CmpLLCwAWB.h		CmpLLCwAWB.h
CmpLLCwPref.h		CmpLLCwPref.h
CmpMCT.h		CmpMCT.h
CmpMSHR.h		CmpMSHR.h
CmpMemoryController.h		CmpMemoryController.h
CmpNextLinePrefetcher.h		CmpNextLinePrefetcher.h
CmpPACManHM.h		CmpPACManHM.h
CmpRTBCache.h		CmpRTBCache.h
CmpSHiPIP.h		CmpSHiPIP.h
CmpSULLC.h		CmpSULLC.h
CmpStall.h		CmpStall.h
CmpStreamPrefetcher.h		CmpStreamPrefetcher.h
CmpStridePrefetcher.h		CmpStridePrefetcher.h
CmpTrace.h		CmpTrace.h
CmpUCP.h		CmpUCP.h
CmpVTSLLC.h		CmpVTSLLC.h
ComponentList.cc		ComponentList.cc
DBI-old.h		DBI-old.h
GenericTable.h		GenericTable.h
GenericTagStore.h		GenericTagStore.h
Makefile		Makefile
Makefile.simics		Makefile.simics
MemoryComponent.h		MemoryComponent.h
MemoryRequest.h		MemoryRequest.h
MemorySchedulers.h		MemorySchedulers.h
MemorySimulator.h		MemorySimulator.h
OoOTraceSimulator.cc		OoOTraceSimulator.cc
OoOTraceSimulator.h		OoOTraceSimulator.h
PolicyList.h		PolicyList.h
README		README
SetDuelingTagStore.h		SetDuelingTagStore.h
SimicsModule.cc		SimicsModule.cc
SimicsSimulator.h		SimicsSimulator.h
SyntheticTrace.h		SyntheticTrace.h
Table.h		Table.h
TableDIP.h		TableDIP.h
TableDRRIP-HP.h		TableDRRIP-HP.h
TableDRRIP.h		TableDRRIP.h
TableFIFO.h		TableFIFO.h
TableGeneration.h		TableGeneration.h
TableLRU.h		TableLRU.h
TableNRU.h		TableNRU.h
TableReuse.h		TableReuse.h
TableSRRIP.h		TableSRRIP.h
TraceReader.h		TraceReader.h
Types.h		Types.h
VictimTagStore.h		VictimTagStore.h
instruction		instruction
new data structures		new data structures
observations		observations
questions		questions

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This is a cache + memory system simulator with a trace-driven input interface. The trace files are not included in the project repository.

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This is a simulator of a cache + memory hierarchy. It has a trace-driven input interface. The trace files are not included in the project.

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