C0

Personal 8-bit RISC cpu written in gate level verilog. Made from the scratch. Even latches are implemented through gates.

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
FallingEdge_Impl		FallingEdge_Impl
Pre-October_2021		Pre-October_2021
RisingEdge_Impl		RisingEdge_Impl
RnD		RnD
OneX_Potato_v3.0.tar.gz		OneX_Potato_v3.0.tar.gz
OneX_Potato_with_Assembler.tar.gz		OneX_Potato_with_Assembler.tar.gz
README		README
README.md		README.md
ROM.v		ROM.v
a.out		a.out
alu.v		alu.v
asm.py		asm.py
asm.pyc		asm.pyc
code.py		code.py
code.v		code.v
control.v		control.v
core.v		core.v
defView.gtkw		defView.gtkw
instrMUX.v		instrMUX.v
manualLoad.v		manualLoad.v
mathComponents.v		mathComponents.v
register.v		register.v
sim.bat		sim.bat
stub.asm		stub.asm
stub.v		stub.v
test.vcd		test.vcd

anotherAsad/C0