ALIGN is an open source automatic layout generator for analog circuits jointly developed under the DARPA IDEA program by the University of Minnesota, Texas A&M University, and Intel Corporation.
The goal of ALIGN (Analog Layout, Intelligently Generated from Netlists) is to automatically translate an unannotated (or partially annotated) SPICE netlist of an analog circuit to a GDSII layout. The repository also releases a set of analog circuit designs.
The ALIGN flow includes the following steps:
- Circuit annotation creates a multilevel hierarchical representation of the input netlist. This representation is used to implement the circuit layout in using a hierarchical manner.
- Design rule abstraction creates a compact JSON-format represetation of the design rules in a PDK. This repository provides a mock PDK based on a FinFET technology (where the parameters are based on published data). These design rules are used to guide the layout and ensure DRC-correctness.
- Primitive cell generation works with primitives, i.e., blocks the lowest level of design hierarchy, and generates their layouts. Primitives typically contain a small number of transistor structures (each of which may be implemented using multiple fins and/or fingers). A parameterized instance of a primitive is automatically translated to a GDSII layout in this step.
- Placement and routing performs block assembly of the hierarchical blocks in the netlist and routes connections between these blocks, while obeying a set of analog layout constraints. At the end of this step, the translation of the input SPICE netlist to a GDSII layout is complete.
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A SPICE netlist of the analog circuit
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- Power and Gnd signals (First power signal is used for global power grid)
- Clk signal (optional)
- Digital blocks (optional)
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Library:(SPICE format)
- A basic built-in template library is provided, which is used to identify hierachies in the design.
- More library elements can be added in the user_template library.
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PDK: Abstracted design rules
- A mock FinFET 14nm PDK rules file is provided, which is used by the primitive cell generator and the place and route engine.
- A new PDK can be represented using a JSON-format design rule abstraction, similar to mock-PDK design rules file provided.
- Primitive cells(NMOS/PMOS/Resistor/Capacitor) must be redefined for any new PDK.
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LEF:
- A list of parameterized cells supported by cell generator is stored in file param_lef.
- Layout GDS: Final layout of the design. The output GDS can be imported into any GDSII viewer.
- Design JSON: Final layout which can be viewed using the ALIGN Viewer.
- Layout image: .jpg format of the layout saved using the KLayout tool.
The suggested way to run the end-to-end ALIGN flow uses a Docker container-based flow for which the user must have docker-compose installed. The ALIGN software is installed in a container image and Make is used to run the flow through the containers. The user may also use the Makefile to run the ALIGN flow through the native Linux build of all the components in the current environment (assuming that all software prerequisites have been installed). Two environment variables must be set to run the Makefile in any environment. The first is the ALIGN_HOME variable, which should point the top directory of the ALIGN analog system.
% export ALIGN_HOME=<top of ALIGN source area>
The second is a working directory ALIGN_WORK_DIR, which can either be the full path to a working directory or a docker volume name.
% docker volume create <volumeName>
% export ALIGN_WORK_DIR=<volumeName for docker flow / full work dir path for native flow>
You can use 'source install.sh' (for bash shell) or 'source install_tcsh.sh' (for tcsh/ Red Hat) to install all the requirements and the native flow. Please go through debug documentation for detailed explanation and common errors during installation.
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Requirements
- Python >= 3.6
- gcc >= 4.2
- Ubuntu >= 18.04/ RedHat
- Boost >= 1.68.0
- Lpsolve >= 5.5.2.5
- JSON >= 3.7.3
- Googletest >= 1.10
- Skip these steps if you are using install.sh
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Setting up local environment variables if installations are not in system search path.
% export BOOST_LP= <boost installation path, e.g., $ALIGN_HOME/boost> % export LP_DIR=<lpsolve installation path, e.g., $ALIGN_HOME/lpsolve> % export JSON= <json installation path, e.g., $ALIGN_HOME/json> % export LD_LIBRARY_PATH=<lpsolve library path, e.g., $ALIGN_HOME/lpsolve/lp_solve_5.5.2.5_dev_ux64/> % export GTEST_DIR=<googletest installation path, e.g., $ALIGN_HOME/googletest/googletest/> % export VENV= <python virtual environment path, e.g., ./align_venv> % Skip these steps if you are using [install.sh](install.sh) -
Installation
% cd PlaceRouteHierFlow % make % cd $ALIGN_HOME % python3 -m venv $VENV % source $VENV/bin/activate % pip install --upgrade pip % pip install -e .
ALIGN also supports push button flow on docker.
- Requirements
- Docker-ce > 17.12
- Docker compose > 3.6
By default, the design directory is set to the examples directory. This can be modified in the Makefile.
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Setup your own work directory
% mkdir $ALIGN_WORK_DIR % cd $ALIGN_WORK_DIR % ln -s $ALIGN_HOME/build/Makefile -
Run your first design "telescopic_ota" on ALIGN
% make VENV=$VENV -
Run different designs from example on ALIGN
% make VENV=$VENV DESIGN=<design> -
Explore different features of ALIGN using python arguments
% source $VENV/bin/activate % schematic2layout.py <input_directory> -f <spice file> -s <design_name> -p <pdk path> -flat <0/1> -c (to check drc) -g (to generate image of layout) % e.g., > schematic2layout.py $ALIGN_HOME/examples/buffer/ -f $ALIGN_HOME/examples/buffer/buffer.sp -s buffer -p $ALIGN_HOME/pdks/FinFET14nm_Mock_PDK -flat 0 -c -g
% cd $ALIGN_HOME/build
% make docker DESIGN=<design>
- examples: Contains example circuits with netlists running on circleci
- CircuitsDatabase: Contains benchmark circuits
The final output GDS can be viewed using by importing in virtuoso or any GDS viewer