def declare_externs(self): """Declare all of the external modules""" self.load_mlir(path.join(thisDir, "esi_load1.mlir")) self.load_mlir(path.join(thisDir, "esi_load2.mlir")) op = hw.HWModuleOp( name='MyWidget', input_ports=[('foo', types.i32), ('foo_valid', types.i1)], output_ports=[('foo_ready', types.i1)], body_builder=lambda module: hw.OutputOp([module.foo_valid])) i32chan = types.chan(types.i32) hw.HWModuleOp(name='I32Snoop', input_ports=[('foo_in', i32chan)], output_ports=[('foo_out', i32chan)], body_builder=lambda module: hw.OutputOp([module.foo_in])) esi.buildWrapper(op.operation, ["foo"])
def build(top): dummy = hw.HWModuleOp(name='dummy', input_ports=[('x', types.i32)], output_ports=[('y', types.i32)], body_builder=lambda mod: {'y': mod.x}) const = hw.ConstantOp.create(types.i32, 0) inst = dummy.create("dummy_inst", x=const.result) try: # CHECK: cannot connect from source of type connect(inst.x, None) except TypeError as e: print(e) try: # CHECK: cannot connect to destination of type connect(None, inst.x) except TypeError as e: print(e)
def top_module(self): return hw.HWModuleOp(name='top', input_ports=[('clk', self.i1), ('rstn', self.i1)], output_ports=[], body_builder=self.build_top)
from mlir.ir import * from mlir.passmanager import PassManager import sys with Context() as ctx, Location.unknown(): circt.register_dialects(ctx) i32 = IntegerType.get_signless(32) m = Module.create() with InsertionPoint(m.body): one_input = hw.HWModuleOp( name="one_input", input_ports=[("a", i32)], body_builder=lambda m: hw.OutputOp([]), ) one_output = hw.HWModuleOp( name="one_output", output_ports=[("a", i32)], body_builder=lambda m: hw.OutputOp( [hw.ConstantOp.create(i32, 46).result]), ) input_output = hw.HWModuleOp( name="input_output", input_ports=[("a", i32)], output_ports=[("b", i32)], body_builder=lambda m: hw.OutputOp([m.a]), )
# CHECK: !hw.struct<foo: i32, bar: !hw.array<5xi32>> struct = hw.StructType.get([("foo", i32), ("bar", array_i32)]) print(struct) # CHECK: !hw.struct<baz: i32, qux: !hw.array<5xi32>> struct = hw.StructType.get([("baz", i32), ("qux", array_i32)]) print(struct) m = Module.create() with InsertionPoint(m.body): # CHECK: hw.module @MyWidget(%my_input: i32) -> (my_output: i32) # CHECK: hw.output %my_input : i32 op = hw.HWModuleOp( name='MyWidget', input_ports=[('my_input', i32)], output_ports=[('my_output', i32)], body_builder=lambda module: hw.OutputOp([module.my_input])) # CHECK: hw.module.extern @FancyThing(%input0: i32) -> (output0: i32) extern = hw.HWModuleExternOp(name="FancyThing", input_ports=[("input0", i32)], output_ports=[("output0", i32)]) one_input = hw.HWModuleOp( name="one_input", input_ports=[("a", i32)], parameters=[ hw.ParamDeclAttr.get("BANKS", TypeAttr.get(i32), IntegerAttr.get(i32, 5)) ],
# CHECK: %reg2 = seq.compreg %[[INPUT_VAL]], %clk reg2 = seq.CompRegOp.create(i32, name="reg2") connect(reg2.input, reg_input) connect(reg2.clk, module.clk) # CHECK: seq.compreg sym @reg1 seq.CompRegOp.create(i32, input=reg_input, clk=module.clk, sym_name="reg1") # CHECK: hw.output %[[DATA_VAL]] hw.OutputOp([reg.data]) hw.HWModuleOp(name="top", input_ports=[("clk", i1), ("rstn", i1)], output_ports=[("result", i32)], body_builder=top) print("=== MLIR ===") print(m) # CHECK-LABEL: === Verilog === print("=== Verilog ===") pm = PassManager.parse("lower-seq-to-sv") pm.run(m) # CHECK: always_ff @(posedge clk) # CHECK: my_reg <= {{.+}} circt.export_verilog(m, sys.stdout)
import circt from circt.support import connect from circt.dialects import hw from circt.esi import types def build(mod, dummy_mod): # CHECK: %[[C0:.+]] = hw.constant 0 const = hw.ConstantOp.create(types.i32, 0) inst = dummy_mod.create("d") connect(inst.x, inst.y) connect(inst.x, const) connect(inst.x, const.result) # CHECK: hw.instance "d" @Dummy(x: %[[C0]]: i32) with mlir.ir.Context() as ctx, mlir.ir.Location.unknown(): circt.register_dialects(ctx) m = mlir.ir.Module.create() with mlir.ir.InsertionPoint(m.body): dummy = hw.HWModuleOp(name='Dummy', input_ports=[("x", types.i32)], output_ports=[("y", types.i32)], body_builder=lambda m: {"y": m.x}) hw.HWModuleOp(name='top', input_ports=[], output_ports=[], body_builder=lambda top: build(top, dummy)) print(m)
import circt from circt.dialects import comb, hw from mlir.ir import Context, Location, InsertionPoint, IntegerType, IntegerAttr, Module with Context() as ctx, Location.unknown(): circt.register_dialects(ctx) i32 = IntegerType.get_signless(32) i31 = IntegerType.get_signless(31) m = Module.create() with InsertionPoint(m.body): def build(module): const1 = hw.ConstantOp(IntegerAttr.get(i32, 1)) const2 = hw.ConstantOp(IntegerAttr.get(i31, 1)) # CHECK: op requires all operands to have the same type div = comb.DivSOp.create(const1.result, const2.result) div.opview.verify() # CHECK: result type cannot be None try: comb.DivSOp.create() except ValueError as e: print(e) hw.HWModuleOp(name="test", body_builder=build)
from circt.dialects import hw from mlir.ir import (Context, Location, InsertionPoint, IntegerType, Module) import io import os with Context() as ctx, Location.unknown(): circt.register_dialects(ctx) i1 = IntegerType.get_signless(1) m = Module.create() with InsertionPoint(m.body): hw.HWModuleOp( name="test", output_ports=[("out", i1)], body_builder=lambda m: {"out": hw.ConstantOp.create(i1, 1)}) buffer = io.StringIO() circt.export_verilog(m, buffer) print(buffer.getvalue()) # INMEMORY: module test( # INMEMORY: output out); # INMEMORY: assign out = 1'h1; # INMEMORY: endmodule cwd = os.getcwd() circt.export_split_verilog(m, cwd) # DIRECTORY: module test( # DIRECTORY: output out); # DIRECTORY: assign out = 1'h1;
def build(top): dummy = hw.HWModuleOp(name='dummy', input_ports=[('x', types.i32)], output_ports=[('y', types.i32)], body_builder=lambda mod: {'y': mod.x}) const = hw.ConstantOp.create(types.i32, 0) inst = dummy.create("dummy_inst", x=const.result) try: # CHECK: cannot connect from source of type connect(inst.x, None) except TypeError as e: print(e) try: # CHECK: cannot connect to destination of type connect(None, inst.x) except TypeError as e: print(e) with mlir.ir.Context() as ctx, mlir.ir.Location.unknown(): circt.register_dialects(ctx) mod = mlir.ir.Module.create() with mlir.ir.InsertionPoint(mod.body): hw.HWModuleOp(name='top', input_ports=[], output_ports=[], body_builder=build)