def __init__(self, toolchain="vivado", programmer="xc3sprog"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
toolchain=toolchain)
if toolchain == "ise":
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
elif toolchain == "vivado":
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
def __init__(self, toolchain="vivado", programmer="vivado"):
XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
except ConstraintError:
pass
def __init__(self, toolchain="vivado", programmer="vivado"):
XilinxPlatform.__init__(self,
"xc7a35ticsg324-1L",
_io,
_connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command(
"set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def __init__(self, variant="50t"):
device = {"50t": "xc7a50tfgg484-1"}[variant]
XilinxPlatform.__init__(self,
device,
_io,
_connectors,
toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command(
"set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def __init__(self, variant="z7-10"):
device = {
"z7-10": "xc7z010-clg400-1",
"z7-20": "xc7z020-clg400-3"
}[variant]
XilinxPlatform.__init__(self,
device,
_io,
_connectors,
toolchain="vivado")
self.default_clk_period = 1e9 / self.default_clk_freq
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
if isinstance(self.toolchain, XilinxISEToolchain):
self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
else:
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def __init__(self):
XilinxPlatform.__init__(self,
"xc7a35tcsg324-2",
_io,
_connectors,
toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16"
" -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
self.add_platform_command(
"set_property CONFIG_VOLTAGE 3.3 [current_design]")
def __init__(self):
XilinxPlatform.__init__(self,
"xc7a100t-fgg676-3",
_io,
toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk200", loose=True),
1e9 / 200e6)
self.add_period_constraint(
self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9 / 125e6)
self.add_period_constraint(
self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9 / 125e6)
self.add_period_constraint(
self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9 / 125e6)
self.add_period_constraint(
self.lookup_request("eth_clocks:tx", 1, loose=True), 1e9 / 125e6)
self.add_platform_command(
"set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def __init__(self,
part,
io,
toolchain="vivado",
programmer="vivado",
make_mod=True):
XilinxPlatform.__init__(self, part, io, toolchain=toolchain)
# NOTE: to do quad-SPI mode, the QE bit has to be set in the SPINOR status register. OpenOCD
# won't do this natively, have to find a work-around (like using iMPACT to set it once)
self.add_platform_command(
"set_property CONFIG_VOLTAGE 1.8 [current_design]")
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
self.add_platform_command(
"set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]")
self.add_platform_command(
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]")
self.toolchain.bitstream_commands = [
"set_property CONFIG_VOLTAGE 1.8 [current_design]",
"set_property CFGBVS GND [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]",
]
self.toolchain.additional_commands = \
["write_cfgmem -verbose -force -format bin -interface spix1 -size 64 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
if make_mod:
for bit in range(0, 32):
for lut in range(4):
if lut == 0:
lutname = 'A'
elif lut == 1:
lutname = 'B'
elif lut == 2:
lutname = 'C'
else:
lutname = 'D'
self.toolchain.additional_commands += [
"set_property INIT 64'hA6C355555555A6C3 [get_cells KEYROM"
+ str(bit) + lutname + "]"
]
self.toolchain.additional_commands += [
"write_bitstream -bin_file -force top-mod.bit"
]
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
except ConstraintError:
pass
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def __init__(self, device="xc7k160tffg676-1", toolchain="vivado"):
XilinxPlatform.__init__(self, device, _io, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command(
"set_property INTERNAL_VREF 0.6 [get_iobanks 32]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.6 [get_iobanks 33]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.6 [get_iobanks 34]")
self.add_platform_command(
"set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7k160t-fbg676-1", _io, _connectors, toolchain=toolchain)
self.add_platform_command("""
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
""")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def main():
parser = argparse.ArgumentParser(description="LiteDRAM standalone core generator")
builder_args(parser)
parser.set_defaults(output_dir="build")
parser.add_argument("config", help="YAML config file")
parser.add_argument("--sim", action='store_true', help="Integrate SDRAMPHYModel in core for simulation")
args = parser.parse_args()
core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
# Convert YAML elements to Python/LiteX --------------------------------------------------------
for k, v in core_config.items():
replaces = {"False": False, "True": True, "None": None}
for r in replaces.keys():
if v == r:
core_config[k] = replaces[r]
if "clk_freq" in k:
core_config[k] = float(core_config[k])
if k == "sdram_module":
core_config[k] = getattr(litedram_modules, core_config[k])
if k == "sdram_phy":
core_config[k] = getattr(litedram_phys, core_config[k])
# Generate core --------------------------------------------------------------------------------
if args.sim:
platform = SimPlatform("", io=[])
elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") # FIXME: allow other devices.
elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
platform = XilinxPlatform("", io=[], toolchain="vivado")
elif core_config["sdram_phy"] in [litedram_phys.USDDRPHY, litedram_phys.USPDDRPHY]:
platform = XilinxPlatform("", io=[], toolchain="vivado")
else:
raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"]))
builder_arguments = builder_argdict(args)
builder_arguments["compile_gateware"] = False
soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x8000)
builder = Builder(soc, **builder_arguments)
builder.build(build_name="litedram_core", regular_comb=False)
if soc.cpu_type is not None:
init_filename = "mem.init"
os.system("mv {} {}".format(
os.path.join(builder.gateware_dir, init_filename),
os.path.join(builder.gateware_dir, "litedram_core.init"),
))
replace_in_file(os.path.join(builder.gateware_dir, "litedram_core.v"), init_filename, "litedram_core.init")
def main():
parser = argparse.ArgumentParser(
description="LitePCIe standalone core generator")
parser.add_argument("config", help="YAML config file")
args = parser.parse_args()
core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
# Convert YAML elements to Python/LiteX --------------------------------------------------------
for k, v in core_config.items():
replaces = {"False": False, "True": True, "None": None}
for r in replaces.keys():
if v == r:
core_config[k] = replaces[r]
# Generate core --------------------------------------------------------------------------------
if core_config["phy"] == "C5PCIEPHY":
from litex.build.altera import AlteraPlatform
from litepcie.phy.c5pciephy import C5PCIEPHY
platform = AlteraPlatform("", io=[])
core_config["phy"] = C5PCIEPHY
core_config["qword_aligned"] = True
core_config["endianness"] = "little"
elif core_config["phy"] == "S7PCIEPHY":
from litex.build.xilinx import XilinxPlatform
from litepcie.phy.s7pciephy import S7PCIEPHY
platform = XilinxPlatform("xc7", io=[], toolchain="vivado")
core_config["phy"] = S7PCIEPHY
core_config["qword_aligned"] = False
core_config["endianness"] = "big"
else:
raise ValueError("Unsupported PCIe PHY: {}".format(core_config["phy"]))
soc = LitePCIeCore(platform, core_config)
builder = Builder(soc, output_dir="build", compile_gateware=False)
vns = builder.build(build_name="litepcie_core", regular_comb=True)
soc.generate_software_headers()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
# DDR4 memory channel C1 Internal Vref
self.add_platform_command(
"set_property INTERNAL_VREF {{0.84}} [get_iobanks 71]")
self.add_platform_command(
"set_property INTERNAL_VREF {{0.84}} [get_iobanks 72]")
self.add_platform_command(
"set_property INTERNAL_VREF {{0.84}} [get_iobanks 73]")
# DDR4 memory channel C2 Internal Vref
self.add_platform_command(
"set_property INTERNAL_VREF {{0.84}} [get_iobanks 40]")
self.add_platform_command(
"set_property INTERNAL_VREF {{0.84}} [get_iobanks 41]")
self.add_platform_command(
"set_property INTERNAL_VREF {{0.84}} [get_iobanks 42]")
def main():
parser = argparse.ArgumentParser(
description="LiteDRAM standalone core generator")
parser.add_argument("config", help="YAML config file")
args = parser.parse_args()
core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
# Convert YAML elements to Python/LiteX --------------------------------------------------------
for k, v in core_config.items():
replaces = {"False": False, "True": True, "None": None}
for r in replaces.keys():
if v == r:
core_config[k] = replaces[r]
if "clk_freq" in k:
core_config[k] = float(core_config[k])
if k == "sdram_module":
core_config[k] = getattr(litedram_modules, core_config[k])
if k == "sdram_phy":
core_config[k] = getattr(litedram_phys, core_config[k])
# Generate core --------------------------------------------------------------------------------
if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
platform = LatticePlatform("", io=[], toolchain="diamond")
elif core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
platform = XilinxPlatform("", io=[], toolchain="vivado")
else:
raise ValueError("Unsupported SDRAM PHY: {}".format(
core_config["sdram_phy"]))
soc = LiteDRAMCore(platform,
core_config,
integrated_rom_size=0x6000,
integrated_sram_size=0x1000)
builder = Builder(soc, output_dir="build", compile_gateware=False)
vns = builder.build(build_name="litedram_core", regular_comb=False)
# Prepare core (could be improved)
def replace_in_file(filename, _from, _to):
# Read in the file
with open(filename, "r") as file:
filedata = file.read()
# Replace the target string
filedata = filedata.replace(_from, _to)
# Write the file out again
with open(filename, 'w') as file:
file.write(filedata)
if soc.cpu_type is not None:
init_filename = "mem.init"
os.system(
"mv build/gateware/{} build/gateware/litedram_core.init".format(
init_filename))
replace_in_file("build/gateware/litedram_core.v", init_filename,
"litedram_core.init")
def __init__(self,
programmer="impact",
device="xc6slx150",
uart_connection="dvi"):
if uart_connection == 'dvi':
_io.append(_dvi_serial)
elif uart_connection == 'hdmi':
_io.append(_hdmi_serial)
else:
raise ValueError(
"Unsupported uart_connection \"{}\", available \"dvi\", \"hdmi\""
.format(uart_connection))
XilinxPlatform.__init__(self, device + "-2-fgg484", _io)
self.programmer = programmer
self.add_platform_command("""CONFIG VCCAUX="2.5";""")
def __init__(self):
XilinxPlatform.__init__(self,
"xc7a35t-ftg256-1",
_io,
toolchain="vivado")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]",
]
self.toolchain.additional_commands = [
"write_bitstream -force -bin_file {build_name}"
]
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self,
"xc7a100t-2fgg484",
_io,
_connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
]
self.toolchain.additional_commands = [
"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"
]
self.add_platform_command(
"set_property INTERNAL_VREF 0.675 [get_iobanks 35]")
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
self.add_platform_command(
"set_property CONFIG_VOLTAGE 3.3 [current_design]")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
# For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
self.add_platform_command(
"set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]"
)
# Reduce programming time
self.add_platform_command(
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
# DDR4 memory channel C0 Clock constraint / Internal Vref
self.add_period_constraint(
self.lookup_request("clk300", 0, loose=True), 1e9 / 300e6)
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 40]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 41]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 42]")
# DDR4 memory channel C1 Clock constraint / Internal Vref
self.add_period_constraint(
self.lookup_request("clk300", 1, loose=True), 1e9 / 300e6)
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 67]")
# DDR4 memory channel C2 Clock constraint / Internal Vref
self.add_period_constraint(
self.lookup_request("clk300", 2, loose=True), 1e9 / 300e6)
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 46]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 47]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 48]")
# DDR4 memory channel C3 Clock constraint / Internal Vref
self.add_period_constraint(
self.lookup_request("clk300", 3, loose=True), 1e9 / 300e6)
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 70]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 71]")
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 72]")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True),
1e9 / 100e6)
self.add_period_constraint(
self.lookup_request("clk100_gtr", loose=True), 1e9 / 100e6)
self.add_period_constraint(
self.lookup_request("clk27_gtr", loose=True), 1e9 / 27e6)
self.add_period_constraint(self.lookup_request("clk33", loose=True),
1e9 / 33e6)
self.add_platform_command(
"set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]"
)
self.add_platform_command(
"set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]"
)
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
def __init__(self):
XilinxPlatform.__init__(self,
"xc7a200t-fbg484-2",
_io,
toolchain="vivado")
self.add_extension(_serial_io)
self.add_extension(_sdcard_io)
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
# Constraint
self.add_period_constraint(self.lookup_request("clk122m88", loose=True), 1e9/122.88e6)
self.add_period_constraint(self.lookup_request("ddram_refclk", 0, loose=True), 1e9/300e6)
self.add_period_constraint(self.lookup_request("ddram_refclk", 1, loose=True), 1e9/300e6)
# VREF for DDR4
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 69]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 70]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 71]")
# Shutdown on overheating
self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
# Reduce programming time
self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
def __init__(self, variant="a7-35", toolchain="vivado"):
device = {
"a7-35": "xc7a35ticsg324-1L",
"a7-100": "xc7a100tcsg324-1"
}[variant]
XilinxPlatform.__init__(self,
device,
_io,
_connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
if toolchain != "yosys+nextpnr": #this is not supported by yosys+pnr
self.add_platform_command(
"set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def __init__(self, variant="s7-50",
toolchain="vivado", programmer="vivado"):
# Arty-S7 is available in two versions with different FPGA devices
device = {
"s7-50": "xc7s50csga324-1",
"s7-25": "xc7s251csga324"
}[variant]
self.device_variant = variant
XilinxPlatform.__init__(self, device, _io, _connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def __init__(self):
XilinxPlatform.__init__(self,
"{}{}".format(device_model, speed_grade),
_io,
_connectors,
toolchain="vivado")
self.add_platform_command("""
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
""")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]",]
self.toolchain.additional_commands = \
["write_cfgmem -force -format mcs -interface SPIx4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.mcs"]
self.speed_grade = speed_grade
def __init__(self, programmer="openocd", vccb2_voltage="VCC3V3"):
# Some IO configurations only work at certain vccb2 voltages.
if vccb2_voltage == "VCC3V3":
_io.extend(_io_vccb2_3v3)
elif vccb2_voltage == "VCC2V5":
_io.extend(_io_vccb2_2v5)
else:
raise SystemError("Unknown vccb2_voltage=%r" % vccb2_voltage)
# Resolve the LVCMOS_BANK2 voltage level before anything uses the _io
# definition.
LVCMOS_BANK2.set(vccb2_voltage)
# XC6SLX45-2CSG324C
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.programmer = programmer
# FPGA AUX is connected to the 3.3V supply on the Atlys
self.add_platform_command("""CONFIG VCCAUX="3.3";""")
def __init__(self, variant="k7-160-2c"):
device = {
"k7-160-2c": "xc7k160tffg676-2",
"k7-325-2c": "xc7k325tfbg676-2"
}[variant]
XilinxPlatform.__init__(self,
device,
_io,
_connectors,
toolchain="vivado")
self.add_platform_command("""
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
""")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def __init__(self):
XilinxPlatform.__init__(self,
"xc7k160t-ffg676-2",
_io,
_connectors,
toolchain="vivado")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
]
self.toolchain.additional_commands = [
"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"
]
# from pin_map.csv: This is a frequency source, not a phase source, so having it enter on a non-CC pin is OK.
self.add_platform_command(
"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk20_IBUF]")
self.add_platform_command(
"set_property CONFIG_VOLTAGE 2.5 [current_design]")
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
def __init__(self, programmer="openocd"):
# XC6SLX45T-3FGG484C
XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors)
self.programmer = programmer
pins = {
'ProgPin': 'PullUp',
'DonePin': 'PullUp',
'TckPin': 'PullNone',
'TdiPin': 'PullNone',
'TdoPin': 'PullNone',
'TmsPin': 'PullNone',
'UnusedPin': 'PullNone',
}
for pin, config in pins.items():
self.toolchain.bitgen_opt += " -g %s:%s " % (pin, config)
# FPGA AUX is connected to the 3.3V supply
self.add_platform_command("""CONFIG VCCAUX="3.3";""")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors,
toolchain="vivado")
def __init__(self, programmer="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, toolchain="vivado")
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def __init__(self, programmer="vivado"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
self.programmer = programmer
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 44]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 45]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 46]")
def __init__(self, device="xc6slx9", programmer="xc3sprog"):
self.programmer = programmer
XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
