def __init__(self, sim: "BasicRtlSimulator", name="Ram_dp"):
BasicRtlSimModel.__init__(self, sim, name=name)
# ports
self.io.a_addr = BasicRtlSimProxy(sim, self, "a_addr", Bits3t(8, 0),
None)
self.io.a_clk = BasicRtlSimProxy(sim, self, "a_clk", Bits3t(1, 0),
None)
self.io.a_din = BasicRtlSimProxy(sim, self, "a_din", Bits3t(64, 0),
None)
self.io.a_dout = BasicRtlSimProxy(sim, self, "a_dout", Bits3t(64, 0),
None)
self.io.a_en = BasicRtlSimProxy(sim, self, "a_en", Bits3t(1, 0), None)
self.io.a_we = BasicRtlSimProxy(sim, self, "a_we", Bits3t(1, 0), None)
self.io.b_addr = BasicRtlSimProxy(sim, self, "b_addr", Bits3t(8, 0),
None)
self.io.b_clk = BasicRtlSimProxy(sim, self, "b_clk", Bits3t(1, 0),
None)
self.io.b_din = BasicRtlSimProxy(sim, self, "b_din", Bits3t(64, 0),
None)
self.io.b_dout = BasicRtlSimProxy(sim, self, "b_dout", Bits3t(64, 0),
None)
self.io.b_en = BasicRtlSimProxy(sim, self, "b_en", Bits3t(1, 0), None)
self.io.b_we = BasicRtlSimProxy(sim, self, "b_we", Bits3t(1, 0), None)
# internal signals
self.io.ram_memory = BasicRtlSimProxy(sim, self, "ram_memory",
self.arr_t_0, None)
self.const_0 = Array3val(self.arr_t_0, {}, 0)
self.const_0_0 = Bits3val(Bits3t(64, 0), 0, 0)
self.const_1_0 = Bits3val(Bits3t(1, 0), 1, 1)
def __init__(self, sim: "BasicRtlSimulator", name="Showcase0"):
BasicRtlSimModel.__init__(self, sim, name=name)
# ports
self.io.a = BasicRtlSimProxy(sim, self, "a", Bits3t(32, 0), None)
self.io.b = BasicRtlSimProxy(sim, self, "b", Bits3t(32, 1), None)
self.io.c = BasicRtlSimProxy(sim, self, "c", Bits3t(32, 0), None)
self.io.clk = BasicRtlSimProxy(sim, self, "clk", Bits3t(1, 0), None)
self.io.cmp_0 = BasicRtlSimProxy(sim, self, "cmp_0", Bits3t(1, 0),
None)
self.io.cmp_1 = BasicRtlSimProxy(sim, self, "cmp_1", Bits3t(1, 0),
None)
self.io.cmp_2 = BasicRtlSimProxy(sim, self, "cmp_2", Bits3t(1, 0),
None)
self.io.cmp_3 = BasicRtlSimProxy(sim, self, "cmp_3", Bits3t(1, 0),
None)
self.io.cmp_4 = BasicRtlSimProxy(sim, self, "cmp_4", Bits3t(1, 0),
None)
self.io.cmp_5 = BasicRtlSimProxy(sim, self, "cmp_5", Bits3t(1, 0),
None)
self.io.contOut = BasicRtlSimProxy(sim, self, "contOut", Bits3t(32, 0),
None)
self.io.d = BasicRtlSimProxy(sim, self, "d", Bits3t(32, 0), None)
self.io.e = BasicRtlSimProxy(sim, self, "e", Bits3t(1, 0), None)
self.io.f = BasicRtlSimProxy(sim, self, "f", Bits3t(1, 0), None)
self.io.fitted = BasicRtlSimProxy(sim, self, "fitted", Bits3t(16, 0),
None)
self.io.g = BasicRtlSimProxy(sim, self, "g", Bits3t(8, 0), None)
self.io.h = BasicRtlSimProxy(sim, self, "h", Bits3t(8, 0), None)
self.io.i = BasicRtlSimProxy(sim, self, "i", Bits3t(2, 0), None)
self.io.j = BasicRtlSimProxy(sim, self, "j", Bits3t(8, 0), None)
self.io.k = BasicRtlSimProxy(sim, self, "k", Bits3t(32, 0), None)
self.io.out = BasicRtlSimProxy(sim, self, "out", Bits3t(1, 0), None)
self.io.output = BasicRtlSimProxy(sim, self, "output", Bits3t(1, 0),
None)
self.io.rst_n = BasicRtlSimProxy(sim, self, "rst_n", Bits3t(1, 0),
None)
self.io.sc_signal = BasicRtlSimProxy(sim, self, "sc_signal",
Bits3t(8, 0), None)
# internal signals
self.const_private_signal = Bits3val(Bits3t(32, 0), 123, 4294967295)
self.io.fallingEdgeRam = BasicRtlSimProxy(sim, self, "fallingEdgeRam",
self.arr_t_0, None)
self.io.r = BasicRtlSimProxy(sim, self, "r", Bits3t(1, 0),
Bits3val(Bits3t(1, 0), 0, 1))
self.io.r_0 = BasicRtlSimProxy(sim, self, "r_0", Bits3t(2, 0),
Bits3val(Bits3t(2, 0), 0, 3))
self.io.r_1 = BasicRtlSimProxy(sim, self, "r_1", Bits3t(2, 0),
Bits3val(Bits3t(2, 0), 0, 3))
self.io.r_next = BasicRtlSimProxy(sim, self, "r_next", Bits3t(1, 0),
None)
self.io.r_next_0 = BasicRtlSimProxy(sim, self, "r_next_0",
Bits3t(2, 0), None)
self.io.r_next_1 = BasicRtlSimProxy(sim, self, "r_next_1",
Bits3t(2, 0), None)
self.rom = Array3val(
self.arr_t_1, {
0: Bits3val(Bits3t(8, 0), 0, 255),
1: Bits3val(Bits3t(8, 0), 1, 255),
2: Bits3val(Bits3t(8, 0), 2, 255),
3: Bits3val(Bits3t(8, 0), 3, 255)
}, 1)
self.const_4_0 = Bits3val(Bits3t(32, 0), 4, 4294967295)
self.const_4_1 = Bits3val(Bits3t(32, 1), 4, 4294967295)
self.const_0 = Array3val(self.arr_t_0, {}, 0)
self.const_0_0 = Bits3val(Bits3t(32, 0), 0, 0)
self.const_1 = slice(8, 0, -1)
self.const_0_1 = Bits3val(Bits3t(24, 0), 0, 16777215)
self.const_2 = slice(16, 0, -1)
self.const_1_0 = Bits3val(Bits3t(32, 1), 1, 4294967295)
self.const_0_2 = Bits3val(Bits3t(32, 1), 0, 4294967295)
self.const_3 = slice(6, 0, -1)
self.const_0_3 = Bits3val(Bits3t(8, 0), 0, 0)
self.const_2_0 = Bits3val(Bits3t(32, 1), 2, 4294967295)
self.const_1_1 = Bits3val(Bits3t(1, 0), 1, 1)
self.const_0_4 = Bits3val(Bits3t(8, 0), 0, 255)
self.const_1_2 = Bits3val(Bits3t(8, 0), 1, 255)
self.const_2_1 = Bits3val(Bits3t(8, 0), 2, 255)
self.const_0_5 = Bits3val(Bits3t(1, 0), 0, 1)
self.const_0_6 = Bits3val(Bits3t(1, 0), 0, 0)
self.const_0_7 = Bits3val(Bits3t(2, 0), 0, 0)
self.const_0_8 = Bits3val(Bits3t(2, 0), 0, 3)
self.const_1_3 = Bits3val(Bits3t(32, 0), 1, 4294967295)
self.const_2_2 = Bits3val(Bits3t(32, 0), 2, 4294967295)
self.const_3_0 = Bits3val(Bits3t(32, 0), 3, 4294967295)
self.const_3_1 = Bits3val(Bits3t(8, 0), 3, 255)
self.const_4_2 = Bits3val(Bits3t(8, 0), 4, 255)