''' Created on Nov 21, 2020 @author: mballance ''' import pybfms @pybfms.bfm(hdl={ pybfms.BfmType.Verilog: pybfms.bfm_hdl_path(__file__, "hdl/wb_initiator_bfm.v"), pybfms.BfmType.SystemVerilog: pybfms.bfm_hdl_path(__file__, "hdl/wb_initiator_bfm.v"), }, has_init=True) class WbInitiatorBfm(): def __init__(self): self.busy = pybfms.lock() self.ack_ev = pybfms.event() self.addr_width = 0 self.data_width = 0 self.reset_ev = pybfms.event() self.is_reset = False async def write(self, adr, dat, sel): await self.busy.acquire() if not self.is_reset: await self.reset_ev.wait() self.reset_ev.clear()
def get_type(self): if self.type in MsgType._value2member_map_: return MsgType(self.type) else: return None def get_mesi(self): if self.mesi in MesiBits._value2member_map_: return MesiBits(self.mesi) else: return None @pybfms.bfm(hdl={ pybfms.BfmType.Verilog: pybfms.bfm_hdl_path(__file__, "hdl/fwnoc_l2_dbg_bfm.v"), pybfms.BfmType.SystemVerilog: pybfms.bfm_hdl_path(__file__, "hdl/fwnoc_l2_dbg_bfm.v") }, has_init=True) class FwNocL2DbgBfm(object): def __init__(self): self.headers = {} self.msgs = {} self.listener = None pass @pybfms.export_task(pybfms.uint8_t, pybfms.uint64_t) def _recv_data(self, noc, data): print("%s [%d]: recv_data 0x%016x" % (self.bfm_info.inst_name, noc, data))
''' Created on Oct 6, 2019 @author: ballance ''' import pybfms @pybfms.bfm(hdl={ pybfms.BfmType.Verilog: pybfms.bfm_hdl_path(__file__, "hdl/rv_data_out_bfm.v"), pybfms.BfmType.SystemVerilog: pybfms.bfm_hdl_path(__file__, "hdl/rv_data_out_bfm.v") }, has_init=True) class ReadyValidDataOutBFM(): def __init__(self): self.busy = pybfms.lock() self.ack_ev = pybfms.event() self.data_width = 0 async def send(self, data): ''' Writes the specified data word to the interface ''' await self.busy.acquire() self._send_req(data) # Wait for acknowledge of the transfer
''' Created on Feb 8, 2021 @author: mballance ''' import pybfms @pybfms.bfm(hdl={ pybfms.BfmType.SystemVerilog: pybfms.bfm_hdl_path(__file__, "hdl/fwperiph_dma_dbg_bfm.v"), pybfms.BfmType.Verilog: pybfms.bfm_hdl_path(__file__, "hdl/fwperiph_dma_dbg_bfm.v") }, has_init=True) class FwPeriphDmaDbgBfm(object): class Channel(object): def __init__(self): self.csr = 0x00000000 self.sz = 0x00000000 self.chk_sz = 0x00000000 self.src = 0x0000000 self.dst = 0x0000000 pass def __init__(self): self.n_channels = 0 self.channels: FwPeriphDmaDbgBfm.Channel = [] for i in range(32): self.channels.append(FwPeriphDmaDbgBfm.Channel()) pass
''' Created on Nov 21, 2020 @author: mballance ''' import pybfms @pybfms.bfm(hdl={ pybfms.BfmType.Verilog : pybfms.bfm_hdl_path(__file__, "hdl/wb_target_bfm.v"), pybfms.BfmType.SystemVerilog : pybfms.bfm_hdl_path(__file__, "hdl/wb_target_bfm.v"), }, has_init=True) class WbTargetBfm(): def __init__(self): self.busy = pybfms.lock() self.ack_ev = pybfms.event() self.addr_width = 0 self.data_width = 0 self.reset_ev = pybfms.event() self.is_reset = False self.responder = None def set_responder(self, responder): self.responder = responder @pybfms.import_task(pybfms.uint64_t,pybfms.uint8_t) def access_ack(self, dat, err): pass
''' Created on Mar 8, 2021 @author: mballance ''' import pybfms from fwnoc_bfms.mem_model import MemModel @pybfms.bfm(hdl={ pybfms.BfmType.SystemVerilog: pybfms.bfm_hdl_path(__file__, "hdl/fwnoc_memtarget_bfm.v"), pybfms.BfmType.Verilog: pybfms.bfm_hdl_path(__file__, "hdl/fwnoc_memtarget_bfm.v") }, has_init=True) class FwNocMemTargetBfm(object): def __init__(self): self.mem = MemModel(32, 64, True) self.count = 0x01010101010101 @pybfms.export_task(pybfms.uint64_t, pybfms.uint64_t) def _write8(self, addr, data): print("memtarget::write8: 0x%08x 0x%08x" % (addr, data)) addr &= 0x3FFFFFFFF self.mem.write_word(addr, (data & 0xFF) | ((data & 0xFF) << 8) | ((data & 0xFF) << 16) | ((data & 0xFF) << 24) | ((data & 0xFF) << 32)
import pybfms @pybfms.bfm(hdl={ pybfms.BfmType.Verilog: pybfms.bfm_hdl_path(__file__, "hdl/rv_addr_line_en_initiator_bfm.v"), pybfms.BfmType.SystemVerilog: pybfms.bfm_hdl_path(__file__, "hdl/rv_addr_line_en_initiator_bfm.v"), }, has_init=True) class RvAddrLineEnInitiatorBfm(): def __init__(self): self.busy = pybfms.lock() self.is_reset = False self.reset_ev = pybfms.event() self.adr_width = 0 self.dat_width = 0 self.ack_ev = pybfms.event() self.dat_r = 0 pass async def write(self, adr, dat): await self.busy.acquire() if not self.is_reset: await self.reset_ev.wait() self.reset_ev.clear() self._access_req(adr, dat, 1) await self.ack_ev.wait()
''' Created on Nov 21, 2020 @author: mballance ''' import pybfms @pybfms.bfm(hdl={ pybfms.BfmType.Verilog : pybfms.bfm_hdl_path(__file__, "hdl/la_initiator_bfm.v"), pybfms.BfmType.SystemVerilog : pybfms.bfm_hdl_path(__file__, "hdl/la_initiator_bfm.v"), }, has_init=True) class LaInitiatorBfm(): def __init__(self): self.busy = pybfms.lock() self.ack_ev = pybfms.event() self.width = 0 self.reset_ev = pybfms.event() self.is_reset = False self.in_data = 0; async def set_bits(self, start, val, mask): await self.busy.acquire() if not self.is_reset: await self.reset_ev.wait() self.reset_ev.clear() self._set_bits(start, val, mask)
import pybfms @pybfms.bfm( hdl={ pybfms.BfmType.Verilog: pybfms.bfm_hdl_path(__file__, "hdl/simple_bfm.sv"), pybfms.BfmType.SystemVerilog: pybfms.bfm_hdl_path(__file__, "hdl/simple_bfm.sv") }) class SimpleBFM(): def __init__(self): print("Hello from init") self.py_task_calls = 0 pass @pybfms.import_task(pybfms.uint32_t) def hdl_task(self, val): pass @pybfms.export_task(pybfms.uint32_t) def py_task(self, val): print("py_task: " + str(val)) self.py_task_calls += 1
''' Created on Oct 8, 2019 @author: ballance ''' import pybfms import os @pybfms.bfm(hdl={ pybfms.BfmType.Verilog: pybfms.bfm_hdl_path(__file__, "hdl/generic_sram_line_en_initiator_bfm.v"), pybfms.BfmType.SystemVerilog: pybfms.bfm_hdl_path(__file__, "hdl/generic_sram_line_en_initiator_bfm.v") }, has_init=True) class GenericSramLineEnInitiatorBFM(object): def __init__(self): self.ADR_WIDTH = 0 self.DAT_WIDTH = 0 self.RD_CYCLES = 0 self.RW_CYCLES = 0 self.busy = pybfms.lock() self.ack_ev = pybfms.event() self.reset_ev = pybfms.event() self.is_reset = False self.read_data = 0 async def write(self, addr, data): await self.busy.acquire()
''' Created on Feb 1, 2020 @author: ballance ''' import pybfms @pybfms.bfm(hdl={ pybfms.BfmType.SystemVerilog: pybfms.bfm_hdl_path(__file__, "hdl/generic_sram_byte_en_dualport_target_bfm.sv"), pybfms.BfmType.Verilog: pybfms.bfm_hdl_path(__file__, "hdl/generic_sram_byte_en_dualport_target_bfm.sv") }, has_init=True) class GenericSramByteEnDualportTargetBFM(): def __init__(self): self.data_width = 0 self.addr_width = 0 self.endian = 0 self.lock = pybfms.lock() self.ack_ev = pybfms.event() self.read_data = None self.mem = [] @pybfms.export_task(pybfms.uint32_t, pybfms.uint32_t) def _set_parameters(self, data_width, addr_width): """Called to set parameter values at initialization"""
from enum import Enum, auto, IntEnum import core_debug_common as cdbgc from core_debug_common.stack_frame import StackFrame import pybfms from riscv_debug_bfms.riscv_params_iterator import RiscvParamsIterator from core_debug_common.callframe_window_mgr import CallframeWindowMgr class RiscvDebugTraceLevel(IntEnum): Call = 0 Jump = 1 All = 2 @pybfms.bfm(hdl={ pybfms.BfmType.Verilog : pybfms.bfm_hdl_path(__file__, "hdl/riscv_debug_bfm.v"), pybfms.BfmType.SystemVerilog : pybfms.bfm_hdl_path(__file__, "hdl/riscv_debug_bfm.v"), }, has_init=True) class RiscvDebugBfm(cdbgc.BfmBase): def __init__(self): super().__init__(32, 32, True) self.busy = pybfms.lock() self.is_reset = False self.reset_ev = pybfms.event() self.en_disasm = True self.window_mgr = CallframeWindowMgr( 8, self._set_func_s,
''' Created on Apr 14, 2021 @author: mballance ''' import pybfms @pybfms.bfm( hdl={ pybfms.BfmType.SystemVerilog : pybfms.bfm_hdl_path(__file__, "share/hdl/uart_bfm.v"), pybfms.BfmType.Verilog : pybfms.bfm_hdl_path(__file__, "share/hdl/uart_bfm.v") }, has_init=True) class UartBfm(object): def __init__(self): self.recv_cb = [] self.tx_busy = pybfms.lock() self.tx_ev = pybfms.event() pass def set_divisor(self, div): self._set_dl(div) def add_recv_cb(self, cb): self.recv_cb.append(cb) def del_recv_cb(self, cb): self.recv_cb.remove(cb) async def recv(self) -> int:
''' Created on Oct 6, 2019 @author: ballance ''' import pybfms @pybfms.bfm(hdl={ pybfms.BfmType.Verilog: pybfms.bfm_hdl_path(__file__, "hdl/rv_data_monitor_bfm.v"), pybfms.BfmType.SystemVerilog: pybfms.bfm_hdl_path(__file__, "hdl/rv_data_monitor_bfm.v") }, has_init=True) class ReadyValidDataMonitorBFM(): def __init__(self): self.listener_l = [] self.data_width = 0 def add_listener(self, l): self.listener_l.append(l) @pybfms.export_task(pybfms.uint64_t) def _data_recv(self, d): for l in self.listener_l: l.data_recv(d) @pybfms.export_task(pybfms.uint64_t) def _set_parameters(self, data_width):