def construct( s, Type, n_ports ): s.in_ = [ InPort( Type ) for _ in range(n_ports) ] s.sel = InPort( mk_bits( clog2(n_ports) ) ) s.out = OutPort( Type ) @s.update def add_upblk(): s.out = s.in_[ s.sel ]
def construct(s, Type, ninputs): s.in_ = [InPort(Type) for _ in range(ninputs)] s.sel = InPort(mk_bits(clog2(ninputs))) s.out = OutPort(Type) @update def up_mux(): s.out @= s.in_[s.sel]
def test_normal_queue_params(do_test): # Test the `params` option of placeholder configs def tv_in(m, tv): m.enq_en = Bits1(tv[0]) m.enq_msg = Bits32(tv[1]) m.deq_en = Bits1(tv[3]) def tv_out(m, tv): if tv[2] != '*': assert m.enq_rdy == Bits1(tv[2]) if tv[4] != '*': assert m.deq_rdy == Bits1(tv[5]) if tv[5] != '*': assert m.deq_msg == Bits32(tv[4]) class Queue(Component, Placeholder): def construct(s, nbits, nelems, nbits_cnt): s.count = OutPort(mk_bits(nbits_cnt)) s.deq_en = InPort(Bits1) s.deq_rdy = OutPort(Bits1) s.deq_msg = OutPort(mk_bits(nbits)) s.enq_en = InPort(Bits1) s.enq_rdy = OutPort(Bits1) s.enq_msg = InPort(mk_bits(nbits)) s.config_placeholder = VerilogPlaceholderConfigs( src_file=dirname(__file__) + '/VQueue.v', top_module='VQueue', params={ 'data_width': nbits, 'num_entries': nelems, 'count_width': nbits_cnt, }, ) s.verilog_translate_import = True num_entries = 1 q = Queue(nbits=32, nelems=num_entries, nbits_cnt=clog2(num_entries + 1)) # q.dump_vcd = True test_vector = [ # enq deq # en msg rdy en msg rdy [1, 42, 1, 0, 0, 0], [0, 43, 0, 1, 42, 1], [1, 43, 1, 0, 42, 0], [0, 44, 0, 1, 43, 1], [1, 44, 1, 0, 43, 0], [0, 45, 0, 1, 44, 1], [1, 45, 1, 0, 44, 0], ] q._test_vectors = test_vector q._tv_in = tv_in q._tv_out = tv_out do_test(q)
def test_normal_queue_interface(do_test): # Test a Placeholder with params in `construct` def tv_in(m, tv): m.enq.en @= Bits1(tv[0]) m.enq.msg @= Bits32(tv[1]) m.deq.en @= Bits1(tv[3]) def tv_out(m, tv): if tv[2] != '*': assert m.enq.rdy == Bits1(tv[2]) if tv[4] != '*': assert m.deq.rdy == Bits1(tv[5]) if tv[5] != '*': assert m.deq.msg == Bits32(tv[4]) class DequeueIfc(Interface): def construct(s, Type): s.en = InPort(Bits1) s.rdy = OutPort(Bits1) s.msg = OutPort(Type) class EnqueueIfc(Interface): def construct(s, Type): s.en = InPort(Bits1) s.rdy = OutPort(Bits1) s.msg = InPort(Type) class VQueue(Component, VerilogPlaceholder): def construct(s, data_width, num_entries, count_width): s.count = OutPort(mk_bits(count_width)) s.deq = DequeueIfc(mk_bits(data_width)) s.enq = EnqueueIfc(mk_bits(data_width)) num_entries = 1 q = VQueue(data_width=32, num_entries=num_entries, count_width=clog2(num_entries + 1)) tv = [ # enq deq # en msg rdy en msg rdy [1, 42, 1, 0, 0, 0], [0, 43, 0, 1, 42, 1], [1, 43, 1, 0, 42, 0], [0, 44, 0, 1, 43, 1], [1, 44, 1, 0, 43, 0], [0, 45, 0, 1, 44, 1], [1, 45, 1, 0, 44, 0], ] q._tvs = tv q._tv_in = tv_in q._tv_out = tv_out do_test(q)
def test_normal_queue_params(do_test): # Test the `params` option of placeholder configs def tv_in(m, tv): m.enq_en @= Bits1(tv[0]) m.enq_msg @= Bits32(tv[1]) m.deq_en @= Bits1(tv[3]) def tv_out(m, tv): if tv[2] != '*': assert m.enq_rdy == Bits1(tv[2]) if tv[4] != '*': assert m.deq_rdy == Bits1(tv[5]) if tv[5] != '*': assert m.deq_msg == Bits32(tv[4]) class Queue(Component, VerilogPlaceholder): def construct(s, nbits, nelems, nbits_cnt): s.count = OutPort(mk_bits(nbits_cnt)) s.deq_en = InPort(Bits1) s.deq_rdy = OutPort(Bits1) s.deq_msg = OutPort(mk_bits(nbits)) s.enq_en = InPort(Bits1) s.enq_rdy = OutPort(Bits1) s.enq_msg = InPort(mk_bits(nbits)) s.set_metadata(VerilogPlaceholderPass.src_file, dirname(__file__) + '/VQueue.v') s.set_metadata(VerilogPlaceholderPass.top_module, 'VQueue') s.set_metadata( VerilogPlaceholderPass.params, { 'data_width': nbits, 'num_entries': nelems, 'count_width': nbits_cnt, }) num_entries = 1 q = Queue(nbits=32, nelems=num_entries, nbits_cnt=clog2(num_entries + 1)) tv = [ # enq deq # en msg rdy en msg rdy [1, 42, 1, 0, 0, 0], [0, 43, 0, 1, 42, 1], [1, 43, 1, 0, 42, 0], [0, 44, 0, 1, 43, 1], [1, 44, 1, 0, 43, 0], [0, 45, 0, 1, 44, 1], [1, 45, 1, 0, 44, 0], ] q._tvs = tv q._tv_in = tv_in q._tv_out = tv_out do_test(q)
def test_normal_queue_implicit_top_module(do_test): # Test a Placeholder with params in `construct` def tv_in(m, tv): m.enq_en = Bits1(tv[0]) m.enq_msg = Bits32(tv[1]) m.deq_en = Bits1(tv[3]) def tv_out(m, tv): if tv[2] != '*': assert m.enq_rdy == Bits1(tv[2]) if tv[4] != '*': assert m.deq_rdy == Bits1(tv[5]) if tv[5] != '*': assert m.deq_msg == Bits32(tv[4]) class VQueue(Component, Placeholder): def construct(s, data_width, num_entries, count_width): s.count = OutPort(mk_bits(count_width)) s.deq_en = InPort(Bits1) s.deq_rdy = OutPort(Bits1) s.deq_msg = OutPort(mk_bits(data_width)) s.enq_en = InPort(Bits1) s.enq_rdy = OutPort(Bits1) s.enq_msg = InPort(mk_bits(data_width)) s.config_placeholder = VerilogPlaceholderConfigs( src_file=dirname(__file__) + '/VQueue.v', ) s.verilog_translate_import = True num_entries = 1 q = VQueue(data_width=32, num_entries=num_entries, count_width=clog2(num_entries + 1)) # q.dump_vcd = True test_vector = [ # enq deq # en msg rdy en msg rdy [1, 42, 1, 0, 0, 0], [0, 43, 0, 1, 42, 1], [1, 43, 1, 0, 42, 0], [0, 44, 0, 1, 43, 1], [1, 44, 1, 0, 43, 0], [0, 45, 0, 1, 44, 1], [1, 45, 1, 0, 44, 0], ] q._test_vectors = test_vector q._tv_in = tv_in q._tv_out = tv_out do_test(q)
def test_normal_queue(do_test): def tv_in(m, tv): m.enq_en = Bits1(tv[0]) m.enq_msg = Bits32(tv[1]) m.deq_en = Bits1(tv[3]) def tv_out(m, tv): if tv[2] != '*': assert m.enq_rdy == Bits1(tv[2]) if tv[4] != '*': assert m.deq_rdy == Bits1(tv[5]) if tv[5] != '*': assert m.deq_msg == Bits32(tv[4]) class VQueue(Placeholder, Component): def construct(s, data_width, num_entries, count_width): s.count = OutPort(mk_bits(count_width)) s.deq_en = InPort(Bits1) s.deq_rdy = OutPort(Bits1) s.deq_msg = OutPort(mk_bits(data_width)) s.enq_en = InPort(Bits1) s.enq_rdy = OutPort(Bits1) s.enq_msg = InPort(mk_bits(data_width)) s.sverilog_import = ImportConfigs(vl_src=get_dir(__file__) + 'VQueue.sv') num_entries = 1 q = VQueue(data_width=32, num_entries=num_entries, count_width=clog2(num_entries + 1)) # q.dump_vcd = True test_vector = [ # enq deq # en msg rdy en msg rdy [1, 42, 1, 0, 0, 0], [0, 43, 0, 1, 42, 1], [1, 43, 1, 0, 42, 0], [0, 44, 0, 1, 43, 1], [1, 44, 1, 0, 43, 0], [0, 45, 0, 1, 44, 1], [1, 45, 1, 0, 44, 0], ] q._test_vectors = test_vector q._tv_in = tv_in q._tv_out = tv_out do_test(q)
def run_test(cls, args, test_vectors): m = cls(*args) T = args[1] Tsel = mk_bits(clog2(args[0])) def tv_in(model, test_vector): n = len(model.in_) for i in range(n): model.in_[i] = T(test_vector[i]) model.sel[i] = Tsel(test_vector[n + i]) def tv_out(model, test_vector): n = len(model.in_) for i in range(n): assert model.out[i] == T(test_vector[n * 2 + i]) m._test_vectors = test_vectors m._tv_in, m._tv_out = tv_in, tv_out do_test(m)
def test_normal_queue(do_test): # Test a Placeholder with params in `construct` def tv_in(m, tv): m.enq_en @= tv[0] m.enq_msg @= tv[1] m.deq_en @= tv[3] def tv_out(m, tv): if tv[2] != '*': assert m.enq_rdy == tv[2] if tv[4] != '*': assert m.deq_rdy == tv[5] if tv[5] != '*': assert m.deq_msg == tv[4] class VQueue(Component, Placeholder): def construct(s, data_width, num_entries, count_width): s.count = OutPort(mk_bits(count_width)) s.deq_en = InPort(Bits1) s.deq_rdy = OutPort(Bits1) s.deq_msg = OutPort(mk_bits(data_width)) s.enq_en = InPort(Bits1) s.enq_rdy = OutPort(Bits1) s.enq_msg = InPort(mk_bits(data_width)) s.set_metadata(VerilogTranslationImportPass.enable, True) num_entries = 1 q = VQueue(data_width=32, num_entries=num_entries, count_width=clog2(num_entries + 1)) tv = [ # enq deq # en msg rdy en msg rdy [1, 42, 1, 0, 0, 0], [0, 43, 0, 1, 42, 1], [1, 43, 1, 0, 42, 0], [0, 44, 0, 1, 43, 1], [1, 44, 1, 0, 43, 0], [0, 45, 0, 1, 44, 1], [1, 45, 1, 0, 44, 0], ] q._tv = tv q._tv_in = tv_in q._tv_out = tv_out do_test(q)
def tv_in( model, test_vector ): for i in range(n_ports): model.in_[i] = Type( test_vector[i] ) model.sel = mk_bits( clog2(n_ports) )( test_vector[n_ports] )