def synthesize(opc): syn = Synthesizer() syn.addInput(BitVecVar('r0', 8)) syn.addInput(BitVecVar('r1', 8)) syn.addInput(BitVecVar('opcode', 2)) r0 = syn.inp('r0') r1 = syn.inp('r1') opcode = syn.inp('opcode') ra = Choice('ra', None, [r0, r1]) add_r = Add(r0, ra) sub_r = Sub(r0, ra) r0_next = Choice('r0_next', None, [add_r, sub_r]) syn.addOutput('r0', r0_next, Synthesizer.BITVEC) syn.debug(vb=2, lf=sys.stdout, uc=True) cnst = Equal(opcode, BitVecVal(opc, 2)) r = syn.synthesize(['r0'], [cnst], alu_sim) print str(r[0]) print '-' * 40
def synAES(st): syn = Synthesizer() createInputs(syn) state = syn.inp('state') addr = syn.inp('addr') length = syn.inp('length') num_op_bytes = syn.inp('num_op_bytes') block_ctr = syn.inp('block_ctr') ctr = syn.inp('ctr') key = syn.inp('key') xram = syn.inp('xram') op = syn.inp('op') addr_in = syn.inp('addr_in') data_in = syn.inp('data_in') aesfns = [syn.inp('AES%d' % i) for i in xrange(16)] addrlist = [BitVecVal(x, 16) for x in [0xFF00, 0xFF01, 0xFF02, 0xFF04, 0xFF10, 0xFF20]] init_state = BitVecVal(0, 1) op_state = BitVecVal(1, 1) in_init_state = Equal(state, init_state) REG_STATE_ADDR = Choice('REG_STATE_ADDR', state, addrlist) REG_START_ADDR = Choice('REG_START_ADDR', state, addrlist) REG_ADDR_ADDR = Choice('REG_ADDR_ADDR', state, addrlist) REG_LEN_ADDR = Choice('REG_LEN_ADDR', state, addrlist) REG_CTR_ADDR = Choice('REG_CTR_ADDR', state, addrlist) REG_KEY_ADDR = Choice('REG_KEY_ADDR', state, addrlist) nop = Equal(op, BitVecVal(0, 2)) rd = Equal(op, BitVecVal(1, 2)) wr = And(in_init_state, Equal(op, BitVecVal(2, 2))) start_out = write1byteReg(wr, addr_in, BitVecVal(0,8), REG_START_ADDR, data_in) addr_out = write2byteReg(wr, addr_in, addr, REG_ADDR_ADDR, data_in) length_out = write2byteReg(wr, addr_in, length, REG_LEN_ADDR, data_in) ctr_out = write16byteReg(wr, addr_in, ctr, REG_CTR_ADDR, data_in) key_out = write16byteReg(wr, addr_in, key, REG_KEY_ADDR, data_in) start = And(wr, Equal(Extract(0, 0, start_out), BitVecVal(1, 1))) num_op_bytes_out = If(in_init_state, If(start, BitVecVal(0, 16), num_op_bytes), Add(num_op_bytes, BitVecVal(16, 16))) more_blocks = ULT(num_op_bytes_out, length) block_ctr_out = If(in_init_state, If(start, BitVecVal(0, 16), block_ctr), If(more_blocks, Add(block_ctr, BitVecVal(16, 16)), block_ctr)) init_state_next = If(start, op_state, init_state) op_state_next = If(more_blocks, op_state, init_state) state_next = If(in_init_state, init_state_next, op_state_next) aes_args = getAESArgs(ctr, key, xram, addr, block_ctr) aes_xram = getUpdatedXram(xram, addr, block_ctr, aes_args, aesfns) xram_out = If(in_init_state, xram, aes_xram) syn.addOutput('addr', addr_out, Synthesizer.BITVEC) syn.addOutput('length', length_out, Synthesizer.BITVEC) syn.addOutput('ctr', ctr_out, Synthesizer.BITVEC) syn.addOutput('key', key_out, Synthesizer.BITVEC) syn.addOutput('num_op_bytes', num_op_bytes_out, Synthesizer.BITVEC) syn.addOutput('block_ctr', block_ctr_out, Synthesizer.BITVEC) syn.addOutput('state', state_next, Synthesizer.BITVEC) syn.addOutput('xram', xram_out, Synthesizer.MEM) cnsts = [ Equal(state, BitVecVal(st, 1)), And(UGT(addr_in, BitVecVal(0xFF00-1, 16)), ULT(addr_in, BitVecVal(0xFF40, 16))) ] outputs = ['addr', 'length', 'ctr', 'key', 'num_op_bytes', 'block_ctr', 'state'] # syn.debug() return syn.synthesize(['addr'], cnsts, evalAES)