def create_ui(self, test_patterns=None, persistent_sim=True): vhdl_path = join(dirname(__file__), "vhdl") ui = VUnit(verbose=True, clean=True, test_filter=make_test_filter(test_patterns), output_path=self.output_path, xunit_xml=self.report_file, persistent_sim=persistent_sim) ui.add_library("lib") ui.add_source_files(join(vhdl_path, "*.vhd"), "lib") return ui
def test_compile_verilog(self): verilog_path = join(dirname(__file__), "verilog") ui = VUnit(verbose=True, clean=True, output_path=self.output_path, xunit_xml=self.report_file, compile_only=True) ui.add_library("lib") ui.add_source_files(join(verilog_path, "*.v"), "lib") ui.add_source_files(join(verilog_path, "*.sv"), "lib") try: ui.main() except SystemExit as e: self.assertEqual(e.code, 0)
def run_sim(self, vhdl_standard): output_path = join(dirname(abspath(__file__)), 'string_ops_out') vhdl_path = join(dirname(abspath(__file__)), '..', 'vhdl') ui = VUnit(clean=True, output_path=output_path, vhdl_standard=vhdl_standard, compile_builtins=False) ui.add_library("lib") ui.add_builtins("vunit_lib", mock_lang=True) ui.add_source_files(join(vhdl_path, "string_ops", "test", "*.vhd"), "lib") try: ui.main() except SystemExit as e: self.assertEqual(e.code, 0)
def _create_ui_real_sim(self, *args): """ Create an instance of the VUnit public interface class """ return VUnit.from_argv( argv=["--output-path=%s" % self._output_path, "--clean"] + list(args), compile_builtins=False, )
def run_sim(self, vhdl_standard): output_path = join(dirname(abspath(__file__)), 'array_out') src_path = join(dirname(abspath(__file__)), '..', 'vhdl', 'array') vu = VUnit(clean=True, output_path=output_path, vhdl_standard=vhdl_standard) vu.add_library("lib") vu.add_array_util("lib") vu.add_source_files(join(src_path, "test", "*.vhd"), "lib") try: vu.main() except SystemExit as e: self.assertEqual(e.code, 0)
def _create_ui(self, *args): """ Create an instance of the VUnit public interface class """ with mock.patch("vunit.ui.SimulatorFactory", new=MockSimulatorFactory): ui = VUnit.from_argv( argv=["--output-path=%s" % self._output_path, "--clean"] + list(args), compile_builtins=False) return ui
def create_vunit(obj, vunit_args, out_basename): # fill vunit arguments args = [] # hack for vunit_compile TCL command if obj['compile']: args += ['--compile'] args += ['--xunit-xml', '../{}.xml1'.format(out_basename)] + list(vunit_args) ui = VUnit.from_argv(args) return ui
def _create_ui(self, *args): """ Create an instance of the VUnit public interface class """ ui = VUnit.from_argv(argv=["--output-path=%s" % self._output_path, "--clean"] + list(args)) ui.add_library("lib") factory = MockSimulatorFactory(self._output_path) self.mocksim = factory.mocksim ui._simulator_factory = factory # pylint: disable=protected-access return ui
def main(): cli = VUnitCLI() cli.parser.add_argument( "--seed", action="store", help="Random seed for the tests", type=int, default=random.randint(-1 << 31, 1 << 31), # VHDL integer range ) args = cli.parse_args() print(f"Seed: {args.seed}") cli = VUnit.from_args(args=args) cli.add_osvvm() cli.enable_location_preprocessing() cli.add_com() if cli.get_simulator_name() == "ghdl": cli.add_preprocessor(GhdlPragmaHandler()) cli.add_library("fpga_cores").add_source_files(p.join( ROOT, "src", "*.vhd")) cli.add_library("str_format").add_source_files( p.join(ROOT, "dependencies", "hdl_string_format", "src", "*.vhd")) cli.add_library("tb") cli.library("tb").add_source_files(p.join(ROOT, "testbench", "*.vhd")) cli.add_library("fpga_cores_sim") cli.library("fpga_cores_sim").add_source_files(p.join( ROOT, "sim", "*.vhd")) cli.add_library("exp_golomb").add_source_files( p.join(ROOT, "src", "exponential_golomb", "*.vhd")) addTests(cli, args.seed) cli.set_compile_option("modelsim.vcom_flags", ["-explicit"]) # Not all options are supported by all GHDL backends # cli.set_compile_option("ghdl.a_flags", ["-frelaxed-rules"]) # cli.set_compile_option("ghdl.a_flags", ["-frelaxed-rules", "-O0", "-g"]) cli.set_compile_option("ghdl.a_flags", ["-frelaxed-rules", "-O2", "-g"]) # Make components not bound (error 3473) an error cli.set_sim_option("modelsim.vsim_flags", ["-error", "3473", '-voptargs="+acc=n"']) # cli.set_sim_option("ghdl.sim_flags", ["-frelaxed-rules"]) # cli.set_sim_option("ghdl.elab_e", ["-frelaxed-rules"]) cli.set_sim_option("ghdl.elab_flags", ["-frelaxed-rules"]) cli.set_sim_option("disable_ieee_warnings", True) cli.set_sim_option("modelsim.init_file.gui", p.join(ROOT, "wave.do")) cli.main()
def _create_ui(self, *args): """ Create an instance of the VUnit public interface class """ ui = VUnit.from_argv( argv=["--output-path=%s" % self._output_path, "--clean"] + list(args), compile_builtins=False) factory = MockSimulatorFactory(self._output_path) self.mocksim = factory.mocksim ui._simulator_factory = factory # pylint: disable=protected-access return ui
def run_sim(self, vhdl_standard): output_path = join(dirname(__file__), "run_out") ui = VUnit(clean=True, output_path=output_path, vhdl_standard=vhdl_standard) ui.add_library("tb_run_lib") vhdl_path = join(dirname(abspath(__file__)), '..', 'vhdl', 'run') ui.add_source_files(join(vhdl_path, 'test', '*.vhd'), "tb_run_lib") try: ui.main() except SystemExit as e: self.assertEqual(e.code, 0)
def run_sim(self, vhdl_standard): output_path = join(dirname(abspath(__file__)), 'logging_out') vhdl_path = join(dirname(abspath(__file__)), '..', 'vhdl', 'logging') ui = VUnit(clean=True, output_path=output_path, vhdl_standard=vhdl_standard, compile_builtins=False) ui.add_builtins('vunit_lib', mock_lang=True) ui.enable_location_preprocessing() lib = ui.add_library('lib') lib.add_source_files(join(vhdl_path, "test", "tb_logging.vhd")) try: ui.main() except SystemExit as e: self.assertEqual(e.code, 0)
def run_sim(self, vhdl_standard): output_path = join(dirname(abspath(__file__)), 'path_out') vhdl_path = join(dirname(abspath(__file__)), '..', 'vhdl') ui = VUnit(clean=True, output_path=output_path, vhdl_standard=vhdl_standard) ui.add_library("lib") ui.add_source_files(join(vhdl_path, "path", "test", "*.vhd"), "lib") try: ui.main() except SystemExit as e: self.assertEqual(e.code, 0)
def main(): "Main entry point for DVB FPGA test runner" _generateGnuRadioData() _createLdpcTables() cli = VUnitCLI() cli.parser.add_argument( "--individual-config-runs", "-i", action="store_true", help="Create individual test runs for each configuration. By default, " "all combinations of frame types, code rates and modulations are " "tested in the same simulation", ) args = cli.parse_args() vunit = VUnit.from_args(args=args) setupSources(vunit) setupTests(vunit, args) vunit.set_compile_option("modelsim.vcom_flags", ["-explicit"]) # Not all options are supported by all GHDL backends vunit.set_sim_option("ghdl.elab_flags", ["-frelaxed-rules"]) vunit.set_compile_option("ghdl.a_flags", ["-frelaxed-rules", "-O2", "-g"]) # Make components not bound (error 3473) an error vsim_flags = ["-error", "3473"] if args.gui: vsim_flags += ['-voptargs="+acc=n"'] vunit.set_sim_option("modelsim.vsim_flags", vsim_flags) vunit.set_sim_option("disable_ieee_warnings", True) vunit.set_sim_option("modelsim.init_file.gui", p.join(ROOT, "wave.do")) vunit.main()
def _create_ui(self): """ Create an instance of the VUnit public interface class """ ui = VUnit.from_argv(argv=["--output-path=%s" % self._output_path, "--clean"]) ui.add_library('lib') return ui
def test_can_add_non_ascii_encoded_files(self): ui = VUnit.from_argv(argv=["--output-path=%s" % self._output_path, "--clean"]) lib = ui.add_library('lib') lib.add_source_files(join(dirname(__file__), 'encoding', 'encoding.vhd')) lib.entity("encoding") # Fill raise exception of not found
def _create_ui(self): ui = VUnit(output_path=self._output_path) ui.add_library('lib') return ui
def run_sim(self, vhdl_standard): output_path = join(dirname(abspath(__file__)), 'check_out') vhdl_path = join(dirname(abspath(__file__)), '..', 'vhdl', 'check', 'test') ui = VUnit(clean=True, output_path=output_path, vhdl_standard=vhdl_standard, compile_builtins=False) ui.add_builtins('vunit_lib', mock_log=True) ui.add_library(r'lib') ui.add_source_files(join(vhdl_path, "test_support.vhd"), 'lib') if vhdl_standard in ('2002', '2008'): ui.add_source_files(join(vhdl_path, "test_count.vhd"), 'lib') ui.add_source_files(join(vhdl_path, "test_types.vhd"), 'lib') elif vhdl_standard == '93': ui.add_source_files(join(vhdl_path, "test_count93.vhd"), 'lib') if vhdl_standard == '2008': ui.add_source_files(join(vhdl_path, "tb_check_relation.vhd"), 'lib', [CheckPreprocessor()]) else: ui.add_source_files( join(vhdl_path, "tb_check_relation93_2002.vhd"), 'lib', [CheckPreprocessor()]) for file_name in glob(join(vhdl_path, "tb_*.vhd")): if basename(file_name) == "tb_check_relation.vhd": continue ui.add_source_files(file_name, 'lib') try: ui.main() except SystemExit as e: self.assertEqual(e.code, 0)
def _create_ui_real_sim(self, *args): """ Create an instance of the VUnit public interface class """ return VUnit.from_argv(argv=["--output-path=%s" % self._output_path, "--clean"] + list(args), compile_builtins=False)