Python aiger_is_input示例

示例#1

文件： aig.py 项目： gaperez64/AbsSynthe

 def get_lit_type(self, lit):
     stripped_lit = strip_lit(lit)
     if (self.error_fake_latch is not None
             and stripped_lit == self.error_fake_latch.lit):
         return None, self.error_fake_latch, None
     input_ = aiger_is_input(self.spec, stripped_lit)
     latch_ = aiger_is_latch(self.spec, stripped_lit)
     and_ = aiger_is_and(self.spec, stripped_lit)
     return input_, latch_, and_

示例#2

文件： aig.py 项目： gaperez64/AbsSynthe

 def get_lit_type(self, lit):
     stripped_lit = strip_lit(lit)
     if (self.error_fake_latch is not None and
             stripped_lit == self.error_fake_latch.lit):
         return None, self.error_fake_latch, None
     input_ = aiger_is_input(self.spec, stripped_lit)
     latch_ = aiger_is_latch(self.spec, stripped_lit)
     and_ = aiger_is_and(self.spec, stripped_lit)
     return input_, latch_, and_

示例#3

文件： synt_2_hwmcc.py 项目： 5nizza/spec-framework

def main(filename):
    #: :type: aiglib.aiger
    model = aiglib.aiger_init()
    aiglib.aiger_open_and_read_from_file(model, filename)

    if model.num_justice == 0:
        _write_result(model)
        return

    assert model.num_justice == 1
    assert model.justice.size == 1

    next_lit = (model.maxvar + 1) * 2

    # first, add all elements

    aiglib.aiger_add_input(model, next_lit, 'SYNT_2_HWMCC_aux')
    #: :type: aiglib.aiger_symbol
    aux = aiglib.aiger_is_input(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and1 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and2 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and3 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and4 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L1')
    #: :type: aiglib.aiger_and
    L1 = aiglib.aiger_is_latch(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L2')
    #: :type: aiglib.aiger_and
    L2 = aiglib.aiger_is_latch(model, next_lit)
    next_lit += 2

    #: :type: aiglib.aiger_symbol
    old_just_lit = aiglib.get_justice_lit(model, 0, 0)

    # second, define all connections
    and1.rhs0, and1.rhs1 = aux.lit + 1, L1.lit + 1
    and2.rhs0, and2.rhs1 = L1.lit, old_just_lit
    and3.rhs0, and3.rhs1 = and2.lhs + 1, L2.lit + 1
    and4.rhs0, and4.rhs1 = L2.lit + 1, L1.lit

    L1.next = and1.lhs + 1
    L2.next = and3.lhs + 1

    aiglib.set_justice_lit(model, 0, 0, and4.lhs)

    #
    _write_result(model)

示例#4

def main(filename):
    #: :type: aiglib.aiger
    model = aiglib.aiger_init()
    aiglib.aiger_open_and_read_from_file(model, filename)

    if model.num_justice == 0:
        _write_result(model)
        return

    assert model.num_justice == 1
    assert model.justice.size == 1

    next_lit = (model.maxvar + 1) * 2

    # first, add all elements

    aiglib.aiger_add_input(model, next_lit, 'SYNT_2_HWMCC_aux')
    #: :type: aiglib.aiger_symbol
    aux = aiglib.aiger_is_input(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and1 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and2 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and3 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and4 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L1')
    #: :type: aiglib.aiger_and
    L1 = aiglib.aiger_is_latch(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L2')
    #: :type: aiglib.aiger_and
    L2 = aiglib.aiger_is_latch(model, next_lit)
    next_lit += 2

    #: :type: aiglib.aiger_symbol
    old_just_lit = aiglib.get_justice_lit(model, 0, 0)

    # second, define all connections
    and1.rhs0, and1.rhs1 = aux.lit + 1, L1.lit + 1
    and2.rhs0, and2.rhs1 = L1.lit, old_just_lit
    and3.rhs0, and3.rhs1 = and2.lhs + 1, L2.lit + 1
    and4.rhs0, and4.rhs1 = L2.lit + 1, L1.lit

    L1.next = and1.lhs + 1
    L2.next = and3.lhs + 1

    aiglib.set_justice_lit(model, 0, 0, and4.lhs)

    #
    _write_result(model)

示例#5

文件： liveness_2_safety.py 项目： 5nizza/spec-framework

def get_lit_type(l):
    input_ = aiglib.aiger_is_input(spec, strip_lit(l))
    latch_ = aiglib.aiger_is_latch(spec, strip_lit(l))
    and_ = aiglib.aiger_is_and(spec, strip_lit(l))

    return input_, latch_, and_

示例#6

文件： liveness_2_safety.py 项目： 5nizza/spec-framework

def get_lit_type(l):
    input_ = aiglib.aiger_is_input(spec, strip_lit(l))
    latch_ = aiglib.aiger_is_latch(spec, strip_lit(l))
    and_ = aiglib.aiger_is_and(spec, strip_lit(l))

    return input_, latch_, and_