class ModuleTracePort(JinjaTempl):
def __init__(self, scfg: StructureConfig):
super().__init__(trim_blocks=True, lstrip_blocks=True)
probes = scfg.digital_probes + scfg.analog_probes + [scfg.time_probe] + [scfg.dec_cmp]
#####################################################
# Define module ios
#####################################################
self.module_ifc = SVAPI()
module = ModuleInst(api=self.module_ifc, name="trace_port_gen")
# Add probe signals
module.add_inputs(probes)
# Add master clk
module.add_input(scfg.emu_clk)
module.generate_header()
#####################################################
# CPU sim control section - add dump statements
#####################################################
self.probe_dumps = SVAPI()
self.probe_dumps.indent()
self.probe_dumps.writeln(f'initial begin')
self.probe_dumps.indent()
self.probe_dumps.writeln('#0;')
for probe in probes:
self.probe_dumps.writeln(f'$dumpvars(0, {probe.name});')
self.probe_dumps.dedent()
self.probe_dumps.writeln(f'end')
#####################################################
# FPGA sim control section - Instantiate ila core
#####################################################
# Instantiate ila core
self.ila_wiz_inst = SVAPI()
ila_wiz = ModuleInst(api=self.ila_wiz_inst, name="ila_0")
for k, signal in enumerate(probes): # Add probe signals
ila_wiz.add_input(DigitalSignal(name=f'probe{k}', abspath=None, width=signal.width), connection=signal)
ila_wiz.add_input(DigitalSignal(name='clk', abspath=None, width=1), connection=scfg.emu_clk) # Add master clk
ila_wiz.generate_instantiation()
TEMPLATE_TEXT = '''
class ModuleEmuClks(JinjaTempl):
def __init__(self, scfg: StructureConfig, pcfg: EmuConfig):
super().__init__(trim_blocks=True, lstrip_blocks=True)
gated_clks = []
#####################################################
# Create module interface
#####################################################
self.module_ifc = SVAPI()
module = ModuleInst(api=self.module_ifc, name="gen_emu_clks")
module.add_input(scfg.emu_clk_2x)
module.add_output(scfg.emu_clk)
for derived_clk in scfg.clk_derived:
if derived_clk.abspath_gated_clk is not None:
gated_clks.append(derived_clk.name)
# add IOs for default oscillator if used
self.use_default_oscillator = scfg.use_default_oscillator
if scfg.use_default_oscillator:
module.add_input(
DigitalSignal(name=f'clk_val_default_osc', width=1,
abspath=''))
module.add_output(
DigitalSignal(name=f'clk_default_osc', width=1, abspath=''))
for gated_clk in gated_clks:
module.add_input(
DigitalSignal(name=f'clk_val_{gated_clk}', width=1,
abspath=''))
module.add_output(
DigitalSignal(name=f'clk_{gated_clk}', width=1, abspath=''))
module.generate_header()
#####################################################
# Generate other clks
#####################################################
self.generated_clks = SVAPI()
if gated_clks:
for gated_clk in gated_clks:
self.generated_clks.gen_signal(DigitalSignal(
name=f'clk_unbuf_{gated_clk}', width=1, abspath=''),
default_value=0)
self.generated_clks.writeln(f'always @(posedge emu_clk_2x) begin')
self.generated_clks.indent()
for gated_clk in gated_clks:
self.generated_clks.writeln(
f"if (emu_clk_unbuf == 1'b0) begin")
self.generated_clks.indent()
self.generated_clks.writeln(
f'clk_unbuf_{gated_clk} <= clk_val_{gated_clk};')
self.generated_clks.dedent()
self.generated_clks.writeln(f'end else begin')
self.generated_clks.indent()
self.generated_clks.writeln(
f"clk_unbuf_{gated_clk} <= clk_unbuf_{gated_clk};")
self.generated_clks.dedent()
self.generated_clks.writeln(f'end')
self.generated_clks.dedent()
self.generated_clks.writeln(f'end')
self.generated_clks.writeln(f'')
self.generated_clks.writeln(f'`ifndef SIMULATION_MODE_MSDSL')
self.generated_clks.indent()
for k, gated_clk in enumerate(gated_clks):
self.generated_clks.writeln(
f'BUFG buf_{k} (.I(clk_unbuf_{gated_clk}), .O(clk_{gated_clk}));'
)
self.generated_clks.dedent()
self.generated_clks.writeln(f'`else')
self.generated_clks.indent()
for gated_clk in gated_clks:
self.generated_clks.writeln(
f'assign clk_{gated_clk} = clk_unbuf_{gated_clk};')
self.generated_clks.dedent()
self.generated_clks.writeln(f'`endif')
TEMPLATE_TEXT = '''