def add_std(cls, target, eem, ttl_out_cls, iostandard="LVDS_25"): cls.add_extension(target, eem, iostandard=iostandard) spi_phy = spi2.SPIMaster(target.platform.request("zotino{}_spi_p".format(eem)), target.platform.request("zotino{}_spi_n".format(eem))) target.submodules += spi_phy target.rtio_channels.append(rtio.Channel.from_phy(spi_phy, ififo_depth=4)) pads = target.platform.request("zotino{}_ldac_n".format(eem)) ldac_phy = ttl_out_cls(pads.p, pads.n) target.submodules += ldac_phy target.rtio_channels.append(rtio.Channel.from_phy(ldac_phy)) pads = target.platform.request("zotino{}_clr_n".format(eem)) clr_phy = ttl_out_cls(pads.p, pads.n) target.submodules += clr_phy target.rtio_channels.append(rtio.Channel.from_phy(clr_phy)) dac_monitor = ad53xx_monitor.AD53XXMonitor(spi_phy.rtlink, ldac_phy.rtlink) target.submodules += dac_monitor spi_phy.probes.extend(dac_monitor.probes)
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) platform = self.platform platform.add_extension(nist_clock.fmc_adapter_io) rtio_channels = [] for i in range(16): if i % 4 == 3: phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append( rtio.Channel.from_phy(phy, ififo_depth=512)) else: phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(2): phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_serdes_7series.InOut_8X( platform.request("user_sma_gpio_n_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) ams101_dac = self.platform.request("ams101_dac", 0) phy = ttl_simple.Output(ams101_dac.ldac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.ClockGen(platform.request("la32_p")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = spi2.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) for i in range(3): phy = spi2.SPIMaster(self.platform.request("spi", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128)) phy = spi2.SPIMaster(platform.request("sdcard_spi_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) fmcdio_dirctl = self.platform.request("fmcdio_dirctl") for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch: phy = ttl_simple.Output(s) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sdac_phy = spi2.SPIMaster(self.platform.request("zotino_spi_p"), self.platform.request("zotino_spi_n")) self.submodules += sdac_phy rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4)) pads = platform.request("zotino_ldac") ldac_phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += ldac_phy rtio_channels.append(rtio.Channel.from_phy(ldac_phy)) dac_monitor = ad53xx_monitor.AD53XXMonitor(sdac_phy.rtlink, ldac_phy.rtlink) self.submodules += dac_monitor sdac_phy.probes.extend(dac_monitor.probes) phy = spi2.SPIMaster(self.platform.request("urukul_spi_p"), self.platform.request("urukul_spi_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split(): pads = platform.request("urukul_{}".format(signal)) phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)