def create_system(self): sc = SysConfig(None, self.mem_size, None) system = FSConfig.makeArmSystem(self.mem_mode, self.machine_type, self.num_cpus, sc, False, ruby=self.use_ruby) # We typically want the simulator to panic if the kernel # panics or oopses. This prevents the simulator from running # an obviously failed test case until the end of time. system.panic_on_panic = True system.panic_on_oops = True default_kernels = { "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", "VExpress_EMM64": "vmlinux.aarch64.20140821", } system.kernel = SysPaths.binary(default_kernels[self.machine_type]) default_dtbs = { "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.{}cpu.dtb" \ .format(self.num_cpus), "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", } system.dtb_filename = SysPaths.binary(default_dtbs[self.machine_type]) self.init_system(system) return system
def create_system(self): if self.aarch64_kernel: gem5_kernel = "vmlinux.arm64" disk_image = "m5_exit.squashfs.arm64" else: gem5_kernel = "vmlinux.arm" disk_image = "m5_exit.squashfs.arm" default_kernels = { "VExpress_GEM5_V1": gem5_kernel, } sc = SysConfig(None, self.mem_size, disk_image, "/dev/sda") system = FSConfig.makeArmSystem(self.mem_mode, self.machine_type, self.num_cpus, sc, False, ruby=self.use_ruby) # We typically want the simulator to panic if the kernel # panics or oopses. This prevents the simulator from running # an obviously failed test case until the end of time. system.panic_on_panic = True system.panic_on_oops = True system.kernel = SysPaths.binary(default_kernels[self.machine_type]) self.init_system(system) system.generateDtb(m5.options.outdir, 'system.dtb') return system
def create_system(self): sc = SysConfig(None, self.mem_size, None) system = FSConfig.makeArmSystem(self.mem_mode, self.machine_type, self.num_cpus, sc, False, ruby=self.use_ruby) # We typically want the simulator to panic if the kernel # panics or oopses. This prevents the simulator from running # an obviously failed test case until the end of time. system.panic_on_panic = True system.panic_on_oops = True default_kernels = { "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", "VExpress_EMM64": "vmlinux.aarch64.20140821", } system.kernel = SysPaths.binary(default_kernels[self.machine_type]) default_dtbs = { "RealViewPBX": None, "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.{}cpu.dtb" \ .format(self.num_cpus), "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", } system.dtb_filename = SysPaths.binary(default_dtbs[self.machine_type]) self.init_system(system) return system
def create_system(self): mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System(self.mem_mode, numCPUs=self.num_cpus, mdesc=mdesc) self.init_system(system) return system
def create_system(self): mdesc = SysConfig(disk='linux-x86.img') system = FSConfig.makeLinuxX86System(self.mem_mode, numCPUs=self.num_cpus, mdesc=mdesc) self.init_system(system) return system
def create(args): # System CpuClass, mem_mode, _ = Simulation.setCPUClass(args) sys_cfg = Benchmarks.SysConfig(args.script, args.mem_size) system = FSConfig.makeArmSystem(mem_mode, "VExpress_GEM5_V2", args.num_cpus, sys_cfg, bare_metal=True, security=True) system.voltage_domain = VoltageDomain(voltage=args.sys_voltage) system.clk_domain = SrcClockDomain(clock=args.sys_clock, voltage_domain=system.voltage_domain) system.highest_el_is_64 = True system.have_virtualization = True system.workload.object_file = args.kernel # CPU cluster system.cpu_voltage_domain = VoltageDomain() system.cpu_clk_domain = SrcClockDomain( clock=args.cpu_clock, voltage_domain=system.cpu_voltage_domain) system.cpu = [ CpuClass(clk_domain=system.cpu_clk_domain, cpu_id=i) for i in range(args.num_cpus) ] for cpu in system.cpu: cpu.createThreads() # (gem5 v20.1) Disable FEAT_VHE, prevents booting features = cpu.isa[0].id_aa64mmfr1_el1.getValue() cpu.isa[0].id_aa64mmfr1_el1 = features & ~0xf00 CacheConfig.config_cache(args, system) # Devices system.realview.atp_adapter = ProfileGen(config_files=args.atp_file, exit_when_done=False, init_only=True, disable_watchdog=True, disable_mem_check=True) system.realview.atp_device = ATPDevice(pio_addr=0x2b500000, interrupt=ArmSPI(num=104), atp_id="STREAM") system.realview.attachSmmu([system.realview.atp_device], system.membus) # (gem5 v20.1) Ensure 128 CMDQ entries for compatibility from Linux v5.4 system.realview.smmu.smmu_idr1 = 0x00E00000 # (gem5 v20.2+) Enable SMMUv3 interrupt interface to boot Linux if hasattr(system.realview.smmu, "irq_interface_enable"): system.realview.smmu.irq_interface_enable = True connect_adapter(system.realview.atp_adapter, system.realview.smmu) if args.disk_image: system.disk = [ PciVirtIO(vio=VirtIOBlock(image=create_cow_image(disk))) for disk in args.disk_image ] for disk in system.disk: system.realview.attachPciDevice(disk, system.iobus) # Memory MemConfig.config_mem(args, system) return system
def create_system(self): mdesc = SysConfig(disks=['linux-x86.img']) system = FSConfig.makeLinuxX86System(self.mem_mode, numCPUs=self.num_cpus, mdesc=mdesc) system.kernel = SysPaths.binary('x86_64-vmlinux-2.6.22.9') self.init_system(system) return system
def create_system(self): sc = SysConfig(None, self.mem_size, None) system = FSConfig.makeArmSystem(self.mem_mode, self.machine_type, self.num_cpus, sc, False) # We typically want the simulator to panic if the kernel # panics or oopses. This prevents the simulator from running # an obviously failed test case until the end of time. system.panic_on_panic = True system.panic_on_oops = True self.init_system(system) return system
def create_system(self): if self.aarch64_kernel: gem5_kernel = "vmlinux.arm64" try: if issubclass(self.cpu_class, ArmV8KvmCPU): disk_image = "m5_exit_addr.squashfs.arm64" else: disk_image = "m5_exit.squashfs.arm64" except: disk_image = "m5_exit.squashfs.arm64" else: gem5_kernel = "vmlinux.arm" disk_image = "m5_exit.squashfs.arm" default_kernels = { "VExpress_GEM5_V1": gem5_kernel, "VExpress_GEM5_Foundation": gem5_kernel, } sc = SysConfig(None, self.mem_size, [disk_image], "/dev/sda") system = FSConfig.makeArmSystem(self.mem_mode, self.machine_type, self.num_cpus, sc, ruby=self.use_ruby) # We typically want the simulator to panic if the kernel # panics or oopses. This prevents the simulator from running # an obviously failed test case until the end of time. system.workload.panic_on_panic = True system.workload.panic_on_oops = True system.workload.object_file = SysPaths.binary( default_kernels[self.machine_type]) self.init_system(system) system.workload.dtb_filename = \ os.path.join(m5.options.outdir, 'system.dtb') system.generateDtb(system.workload.dtb_filename) return system
(options, args) = parser.parse_args() # Set the default cache size and associativity to be very small to encourage # races between requests and writebacks. options.l1d_size = "32kB" options.l1i_size = "32kB" options.l2_size = "4MB" options.l1d_assoc = 2 options.l1i_assoc = 2 options.l2_assoc = 2 options.num_cpus = 2 #the system mdesc = SysConfig(disk='linux-x86.img') system = FSConfig.makeLinuxX86System('timing', options.num_cpus, mdesc=mdesc, Ruby=True) system.kernel = SysPaths.binary('x86_64-vmlinux-2.6.22.9') # Dummy voltage domain for all our clock domains system.voltage_domain = VoltageDomain(voltage=options.sys_voltage) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') system.clk_domain = SrcClockDomain(clock='1GHz', voltage_domain=system.voltage_domain) system.cpu_clk_domain = SrcClockDomain(clock='2GHz', voltage_domain=system.voltage_domain) system.cpu = [ TimingSimpleCPU(cpu_id=i, clk_domain=system.cpu_clk_domain) for i in range(options.num_cpus) ]
def build(options): m5.ticks.fixGlobalFrequency() kernel_cmd = [ "earlyprintk", "earlycon=pl011,0x1c090000", "console=ttyAMA0", "lpj=19988480", "norandmaps", "loglevel=8", "mem=%s" % options.mem_size, "root=%s" % options.root, "rw", "init=%s" % options.kernel_init, "vmalloc=768MB", ] root = Root(full_system=True) disks = [default_disk] if len(options.disk) == 0 else options.disk system = createSystem(options.caches, options.kernel, options.bootscript, options.machine_type, disks=disks, mem_size=options.mem_size, bootloader=options.bootloader) root.system = system if options.kernel_cmd: system.workload.command_line = options.kernel_cmd else: system.workload.command_line = " ".join(kernel_cmd) if options.big_cpus + options.little_cpus == 0: m5.util.panic("Empty CPU clusters") big_model, little_model = cpu_types[options.cpu_type] all_cpus = [] # big cluster if options.big_cpus > 0: system.bigCluster = big_model(system, options.big_cpus, options.big_cpu_clock) system.mem_mode = system.bigCluster.memoryMode() all_cpus += system.bigCluster.cpus # little cluster if options.little_cpus > 0: system.littleCluster = little_model(system, options.little_cpus, options.little_cpu_clock) system.mem_mode = system.littleCluster.memoryMode() all_cpus += system.littleCluster.cpus # Figure out the memory mode if options.big_cpus > 0 and options.little_cpus > 0 and \ system.bigCluster.memoryMode() != system.littleCluster.memoryMode(): m5.util.panic("Memory mode missmatch among CPU clusters") # create caches system.addCaches(options.caches, options.last_cache_level) if not options.caches: if options.big_cpus > 0 and system.bigCluster.requireCaches(): m5.util.panic("Big CPU model requires caches") if options.little_cpus > 0 and system.littleCluster.requireCaches(): m5.util.panic("Little CPU model requires caches") # Create a KVM VM and do KVM-specific configuration if issubclass(big_model, KvmCluster): _build_kvm(system, all_cpus) # Linux device tree if options.dtb is not None: system.workload.dtb_filename = SysPaths.binary(options.dtb) else: system.workload.dtb_filename = \ os.path.join(m5.options.outdir, 'system.dtb') system.generateDtb(system.workload.dtb_filename) if devices.have_fastmodel and issubclass(big_model, FastmodelCluster): from m5 import arm_fast_model as fm, systemc as sc # setup FastModels for simulation fm.setup_simulation("cortexa76") # setup SystemC root.systemc_kernel = m5.objects.SystemC_Kernel() m5.tlm.tlm_global_quantum_instance().set( sc.sc_time(10000.0 / 100000000.0, sc.sc_time.SC_SEC)) if options.vio_9p: FSConfig.attach_9p(system.realview, system.iobus) return root
def create_system(self): system = FSConfig.makeLinuxAlphaSystem(self.mem_mode) self.init_system(system) return system
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Lisa Hsu import m5 from m5.objects import * m5.util.addToPath('../configs/') from common import Benchmarks, FSConfig, SysPaths test_sys = FSConfig.makeLinuxAlphaSystem('atomic', Benchmarks.SysConfig('netperf-stream-client.rcS')) test_sys.kernel = SysPaths.binary('vmlinux') # Dummy voltage domain for all test_sys clock domains test_sys.voltage_domain = VoltageDomain() # Create the system clock domain test_sys.clk_domain = SrcClockDomain(clock = '1GHz', voltage_domain = test_sys.voltage_domain) test_sys.cpu = AtomicSimpleCPU(cpu_id=0) # create the interrupt controller test_sys.cpu.createInterruptController() test_sys.cpu.connectAllPorts(test_sys.membus) # Create a seperate clock domain for components that should run at
def build(options): m5.ticks.fixGlobalFrequency() kernel_cmd = [ "earlyprintk=pl011,0x1c090000", "console=ttyAMA0", "lpj=19988480", "norandmaps", "loglevel=8", "mem=%s" % options.mem_size, "root=%s" % options.root, "rw", "init=%s" % options.kernel_init, "vmalloc=768MB", ] root = Root(full_system=True) disks = [default_disk] if len(options.disk) == 0 else options.disk system = createSystem(options.caches, options.kernel, options.bootscript, options.machine_type, disks=disks, mem_size=options.mem_size, bootloader=options.bootloader) root.system = system if options.kernel_cmd: system.boot_osflags = options.kernel_cmd else: system.boot_osflags = " ".join(kernel_cmd) if options.big_cpus + options.little_cpus + options.mid_cpus == 0: m5.util.panic("Empty CPU clusters") big_model, mid_model, little_model = cpu_types[options.cpu_type] sw_big_cpu, sw_mid_cpu, sw_little_cpu = sw_cpu_types[options.sw_cpu_type] all_cpus = [] sw_all_cpus = [] if options.big_cpus > 0: system.bigCluster = big_model(system, options.big_cpus, options.big_cpu_clock) system.mem_mode = system.bigCluster.memoryMode() all_cpus += system.bigCluster.cpus cpu_class_tmp = ObjectList.cpu_list.get(sw_big_cpu) big_sw_cpus = [ cpu_class_tmp(switched_out=True, cpu_id=(i)) for i in range(options.big_cpus) ] for i in range(options.big_cpus): if options.fast_forward: system.bigCluster.cpus[i].max_insts_any_thread = int( options.fast_forward) big_sw_cpus[i].system = system big_sw_cpus[i].workload = system.bigCluster.cpus[i].workload big_sw_cpus[i].clk_domain = system.bigCluster.cpus[i].clk_domain big_sw_cpus[i].progress_interval = system.bigCluster.cpus[ i].progress_interval big_sw_cpus[i].isa = system.bigCluster.cpus[i].isa system.bigCluster.switch_cpus = big_sw_cpus if options.mid_cpus > 0: system.midCluster = mid_model(system, options.mid_cpus, options.mid_cpu_clock) system.mem_mode = system.midCluster.memoryMode() all_cpus += system.midCluster.cpus cpu_class_tmp = ObjectList.cpu_list.get(sw_mid_cpu) mid_sw_cpus = [ cpu_class_tmp(switched_out=True, cpu_id=(i + options.big_cpus)) for i in range(options.mid_cpus) ] for i in range(options.mid_cpus): if options.fast_forward: system.midCluster.cpus[i].max_insts_any_thread = int( options.fast_forward) mid_sw_cpus[i].system = system mid_sw_cpus[i].workload = system.midCluster.cpus[i].workload mid_sw_cpus[i].clk_domain = system.midCluster.cpus[i].clk_domain mid_sw_cpus[i].progress_interval = system.midCluster.cpus[ i].progress_interval mid_sw_cpus[i].isa = system.midCluster.cpus[i].isa system.midCluster.switch_cpus = mid_sw_cpus if options.little_cpus > 0: system.littleCluster = little_model(system, options.little_cpus, options.little_cpu_clock) system.mem_mode = system.littleCluster.memoryMode() all_cpus += system.littleCluster.cpus cpu_class_tmp = ObjectList.cpu_list.get(sw_little_cpu) little_sw_cpus = [ cpu_class_tmp(switched_out=True, cpu_id=(i + options.big_cpus + options.mid_cpus)) for i in range(options.little_cpus) ] for i in range(options.little_cpus): if options.fast_forward: system.littleCluster.cpus[i].max_insts_any_thread = int( options.fast_forward) little_sw_cpus[i].system = system little_sw_cpus[i].workload = system.littleCluster.cpus[i].workload little_sw_cpus[i].clk_domain = system.littleCluster.cpus[ i].clk_domain little_sw_cpus[i].progress_interval = system.littleCluster.cpus[ i].progress_interval little_sw_cpus[i].isa = system.littleCluster.cpus[i].isa system.littleCluster.switch_cpus = little_sw_cpus system.addCaches(options.caches) if not options.caches: if options.big_cpus > 0 and system.bigCluster.requireCaches(): m5.util.panic("Big CPU model requires caches") if options.mid_cpus > 0 and system.bigCluster.requireCaches(): m5.util.panic("Mid CPU model requires caches") if options.little_cpus > 0 and system.littleCluster.requireCaches(): m5.util.panic("Little CPU model requires caches") if issubclass(big_model, KvmCluster): _build_kvm(system, all_cpus) # Linux device tree if options.dtb is not None: system.dtb_filename = SysPaths.binary(options.dtb) else: system.generateDtb(m5.options.outdir, 'system.dtb') if options.vio_9p: FSConfig.attach_9p(system.realview, system.iobus) return root
Ruby.define_options(parser) (options, args) = parser.parse_args() # Set the default cache size and associativity to be very small to encourage # races between requests and writebacks. options.l1d_size="32kB" options.l1i_size="32kB" options.l2_size="4MB" options.l1d_assoc=2 options.l1i_assoc=2 options.l2_assoc=2 options.num_cpus = 2 #the system mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('timing', options.num_cpus, mdesc=mdesc, Ruby=True) # Dummy voltage domain for all our clock domains system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') system.clk_domain = SrcClockDomain(clock = '1GHz', voltage_domain = system.voltage_domain) system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', voltage_domain = system.voltage_domain) system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain) for i in xrange(options.num_cpus)] Ruby.create_system(options, True, system, system.iobus, system._dma_ports) # Create a seperate clock domain for Ruby system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi import m5 from m5.objects import * m5.util.addToPath('../configs/') from common import FSConfig try: system = FSConfig.makeSparcSystem('atomic') except IOError as e: skip_test(reason=str(e)) system.voltage_domain = VoltageDomain() system.clk_domain = SrcClockDomain(clock='1GHz', voltage_domain=system.voltage_domain) system.cpu_clk_domain = SrcClockDomain(clock='1GHz', voltage_domain=system.voltage_domain) cpu = AtomicSimpleCPU(cpu_id=0, clk_domain=system.cpu_clk_domain) system.cpu = cpu # create the interrupt controller cpu.createInterruptController() cpu.connectAllPorts(system.membus) # create the memory controllers and connect them, stick with
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi import m5 from m5.objects import * m5.util.addToPath('../configs/') from common import FSConfig try: system = FSConfig.makeSparcSystem('atomic') except IOError as e: skip_test(reason=str(e)) system.voltage_domain = VoltageDomain() system.clk_domain = SrcClockDomain(clock = '1GHz', voltage_domain = system.voltage_domain) system.cpu_clk_domain = SrcClockDomain(clock = '1GHz', voltage_domain = system.voltage_domain) cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain) system.cpu = cpu # create the interrupt controller cpu.createInterruptController() cpu.connectAllPorts(system.membus) # create the memory controllers and connect them, stick with
def create_system(self): system = FSConfig.makeLinuxAlphaSystem(self.mem_mode) system.kernel = SysPaths.binary('vmlinux') self.init_system(system) return system
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Lisa Hsu import m5 from m5.objects import * m5.util.addToPath('../configs/') from common import Benchmarks, FSConfig, SysPaths test_sys = FSConfig.makeLinuxAlphaSystem( 'atomic', Benchmarks.SysConfig('netperf-stream-client.rcS')) test_sys.kernel = SysPaths.binary('vmlinux') # Dummy voltage domain for all test_sys clock domains test_sys.voltage_domain = VoltageDomain() # Create the system clock domain test_sys.clk_domain = SrcClockDomain(clock='1GHz', voltage_domain=test_sys.voltage_domain) test_sys.cpu = AtomicSimpleCPU(cpu_id=0) # create the interrupt controller test_sys.cpu.createInterruptController() test_sys.cpu.connectAllPorts(test_sys.membus) # Create a seperate clock domain for components that should run at