def build(cls, unit: Unit, unique_name: str, build_dir: Optional[str], target_platform=DummyPlatform(), do_compile=True) -> "BasicRtlSimulatorVcd": """ Create a pycocotb.basic_hdl_simulator based simulation model for specified unit and load it to python :param unit: interface level unit which you wont prepare for simulation :param unique_name: unique name for build directory and python module with simulator :param target_platform: target platform for this synthesis :param build_dir: directory to store sim model build files, if None sim model will be constructed only in memory """ if unique_name is None: unique_name = unit._getDefaultName() _filter = SerializerFilterDoNotExclude() if build_dir is None or not do_compile: buff = StringIO() store_man = SaveToStream(SimModelSerializer, buff, _filter=_filter) else: if not os.path.isabs(build_dir): build_dir = os.path.join(os.getcwd(), build_dir) build_private_dir = os.path.join(build_dir, unique_name) store_man = SaveToFilesFlat(SimModelSerializer, build_private_dir, _filter=_filter) store_man.module_path_prefix = unique_name to_rtl(unit, name=unique_name, target_platform=target_platform, store_manager=store_man) if build_dir is not None: d = build_dir dInPath = d in sys.path if not dInPath: sys.path.insert(0, d) if unique_name in sys.modules: del sys.modules[unique_name] simModule = importlib.import_module( unique_name + "." + unique_name, package='simModule_' + unique_name) if not dInPath: sys.path.pop(0) else: simModule = ModuleType('simModule_' + unique_name) # python supports only ~100 opened brackets # if exceeded it throws MemoryError: s_push: parser stack overflow exec(buff.getvalue(), simModule.__dict__) model_cls = simModule.__dict__[unit._name] # can not use just function as it would get bounded to class return cls(model_cls, unit)
def toBasicSimulatorSimModel(unit: Unit, unique_name: str, build_dir: Optional[str], target_platform=DummyPlatform(), do_compile=True): """ Create a pycocotb.basic_hdl_simulator based simulation model for specified unit and load it to python :param unit: interface level unit which you wont prepare for simulation :param unique_name: unique name for build directory and python module with simulator :param target_platform: target platform for this synthesis :param build_dir: directory to store sim model build files, if None sim model will be constructed only in memory """ if unique_name is None: unique_name = unit._getDefaultName() if build_dir is not None: build_private_dir = os.path.join(os.getcwd(), build_dir, unique_name) else: build_private_dir = None sim_code = toRtl(unit, name=unique_name, targetPlatform=target_platform, saveTo=build_private_dir, serializer=SimModelSerializer) if build_dir is not None: d = os.path.join(os.getcwd(), build_dir) dInPath = d in sys.path if not dInPath: sys.path.insert(0, d) if unique_name in sys.modules: del sys.modules[unique_name] simModule = importlib.import_module(unique_name + "." + unique_name, package='simModule_' + unique_name) if not dInPath: sys.path.pop(0) else: simModule = ModuleType('simModule_' + unique_name) # python supports only ~100 opened brackets # if exceded it throws MemoryError: s_push: parser stack overflow exec(sim_code, simModule.__dict__) model_cls = simModule.__dict__[unit._name] # can not use just function as it would get bounded to class return BasicSimConstructor(model_cls, unit)
def compileSimAndStart(self, unit: Unit, build_dir: Optional[str] = DEFAULT_BUILD_DIR, unique_name: Optional[str] = None, onAfterToRtl=None, target_platform=DummySimPlatform()): """ Use this method if you did not used compileSim() or SingleUnitSimTestCase to setup the simulator and DUT """ if unique_name is None: unique_name = "%s__%s" % (self.getTestName(), unit._getDefaultName()) self.compileSim(unit, build_dir, unique_name, onAfterToRtl, target_platform) self.u = unit SimTestCase.setUp(self) return self.u
def __init__(self, topUnit: Unit, name: str=None, extra_files: List[str]=[], serializer_cls=Vhdl2008Serializer, target_platform=DummyPlatform()): """ :param topObj: :class:`hwt.synthesizer.unit.Unit` instance of top component :param name: optional name of top :param extra_files: list of extra HDL/constrain file names for files which should be distributed in this IP-core (\*.v - verilog, \*.sv,\*.svh -system verilog, \*.vhd - vhdl, \*.xdc - XDC) :param serializer: serializer which specifies target HDL language :param target_platform: specifies properties of target platform, like available resources, vendor, etc. """ if not name: name = topUnit._getDefaultName() super(IpPackager, self).__init__( topUnit, name, extra_files) self.serializer = serializer_cls self.target_platform = target_platform
def __init__(self, topUnit: Unit, name: str=None, extraVhdlFiles: List[str]=[], extraVerilogFiles: List[str]=[], serializer=VhdlSerializer, targetPlatform=DummyPlatform()): """ :param topObj: Unit instance of top component :param name: optional name of top :param extraVhdlFiles: list of extra vhdl file names for files which should be distributed in this IP-core :param extraVerilogFiles: same as extraVhdlFiles just for Verilog :param serializer: serializer which specifies target HDL language :param targetPlatform: specifies properties of target platform, like available resources, vendor, etc. """ assert not topUnit._wasSynthetised() if not name: name = topUnit._getDefaultName() super(IpPackager, self).__init__( topUnit, name, extraVhdlFiles, extraVerilogFiles) self.serializer = serializer self.targetPlatform = targetPlatform
def get_unique_name(cls, unit: Unit): uniq_name = unit._getDefaultName() return f"{cls.__name__:s}__{uniq_name:s}"
def get_unique_name(cls, unit: Unit): return "%s__%s" % (cls.__name__, unit._getDefaultName())