def __init__(self, sys_clk_freq=int(80e6), **kwargs): platform = minispartan6.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy=self.sdrphy, module=AS4C16M16(sys_clk_freq, "1:1"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(8)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(80e6), sdram_rate="1:1", **kwargs): platform = minispartan6.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MiniSpartan6", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) self.add_sdram("sdram", phy=self.sdrphy, module=AS4C16M16(sys_clk_freq, sdram_rate), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, **kwargs): platform = minispartan6.Platform() sys_clk_freq = int(80e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform, sys_clk_freq) if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = AS4C16M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(80e6), **kwargs): assert sys_clk_freq == int(80e6) platform = minispartan6.Platform() # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = AS4C16M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(8e6)): platform = minispartan6.Platform() platform.add_extension(scope_io) SoCMini.__init__(self, platform, clk_freq=sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq) # led counter = Signal(32) self.sync += counter.eq(counter + 1) self.comb += platform.request("user_led", 0).eq(counter[26]) # scope self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC", i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1, i_C0=ClockSignal("sys"), i_C1=~ClockSignal("sys"), o_Q=platform.request("scope0")) self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC", i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1, i_C0=ClockSignal("sys_ps"), i_C1=~ClockSignal("sys_ps"), o_Q=platform.request("scope1"))
def __init__(self, with_cpu, with_emulator, with_analyzer): platform = minispartan6.Platform(device="xc6slx25") platform.add_extension(_sd_io) clk_freq = int(50e6) sd_freq = int(140e6) SoCCore.__init__(self, platform, clk_freq=clk_freq, cpu_type="lm32" if with_cpu else None, csr_data_width=32, with_uart=with_cpu, with_timer=with_cpu, ident="SDCard Test SoC", ident_version=True, integrated_rom_size=0x8000 if with_cpu else 0, integrated_main_ram_size=0x8000 if with_cpu else 0) self.submodules.crg = _CRG(platform, clk_freq) # bridge if not with_cpu: self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) # emulator if with_emulator: sdcard_pads = _sdemulator_pads() self.submodules.sdemulator = SDEmulator(platform, sdcard_pads) else: sdcard_pads = platform.request('sdcard') # sd self.submodules.sdclk = SDClockerS6() self.submodules.sdphy = SDPHY(sdcard_pads, platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9 / sd_freq) self.crg.cd_sys.clk.attr.add("keep") self.sdclk.cd_sd.clk.attr.add("keep") self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.sdclk.cd_sd.clk) # led led_counter = Signal(32) self.sync.sd += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led", 0).eq(led_counter[26]) # analyzer if with_analyzer: analyzer_signals = [ self.sdphy.sdpads, self.sdphy.cmdw.sink, self.sdphy.cmdr.sink, self.sdphy.cmdr.source, self.sdphy.dataw.sink, self.sdphy.datar.sink, self.sdphy.datar.source ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 2048, cd="sd", cd_ratio=4)
def __init__(self, with_cpu, with_emulator, with_analyzer): platform = minispartan6.Platform(device="xc6slx25") sys_clk_freq = int(50e6) sd_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq = sys_clk_freq, cpu_type = "vexriscv" if with_cpu else None, csr_data_width = 32, with_uart = with_cpu, with_timer = with_cpu, ident = "SDCard Test SoC", ident_version = True, integrated_rom_size = 0x8000 if with_cpu else 0, integrated_main_ram_size = 0x8000 if with_cpu else 0 )s # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Serial bridge (optional) ----------------------------------------------------------------- if not with_cpu: self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq) self.add_wb_master(self.bridge.wishbone) # SDCard Emulator (optional) --------------------------------------------------------------- if with_emulator: from litesdcard.emulator import SDEmulator, _sdemulator_pads sdcard_pads = _sdemulator_pads() self.submodules.sdemulator = SDEmulator(platform, sdcard_pads) self.add_csr("sdemulator") else: sdcard_pads = platform.request('sdcard') # SDCard ----------------------------------------------------------------------------------- self.submodules.sdclk = SDClockerS6() self.submodules.sdphy = SDPHY(sdcard_pads, platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.add_csr("sdclk") self.add_csr("sdphy") self.add_csr("sdcore") self.add_csr("sdtimer") self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.add_csr("bist_generator") self.add_csr("bist_checker") self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_clk_freq) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.sdclk.cd_sd.clk) # Led -------------------------------------------------------------------------------------- led_counter = Signal(32) self.sync.sd += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led", 0).eq(led_counter[26]) # Analyzer (optional) ---------------------------------------------------------------------- if with_analyzer: from litescope import LiteScopeAnalyzer analyzer_signals = [ self.sdphy.sdpads, self.sdphy.cmdw.sink, self.sdphy.cmdr.sink, self.sdphy.cmdr.source, self.sdphy.dataw.sink, self.sdphy.datar.sink, self.sdphy.datar.source ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 2048, clock_domain="sd", csr_csv="../test/analyzer.csv") self.add_csr("analyzer")