def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", **kwargs): platform = ecp5_evn.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_main_ram_size=0x8000, **kwargs) # CRG -------------------------------------------------------------------------------------- crg = _CRG(platform, sys_clk_freq, x5_clk_freq) self.submodules.crg = crg # HyperRam -------------------------------------------------------------------------------- self.submodules.hyperram = HyperRAM(platform.request("hyperram")) self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus) self.add_memory_region("hyperram", self.mem_map["hyperram"], 8 * 1024 * 1024) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(8)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", with_led_chaser=True, **kwargs): platform = ecp5_evn.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECP5 Evaluation Board", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- crg = _CRG(platform, sys_clk_freq, x5_clk_freq) self.submodules.crg = crg # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", **kwargs): platform = ecp5_evn.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on ECP5 Evaluation Board", ident_version = True, integrated_main_ram_size=0x8000, **kwargs) # CRG -------------------------------------------------------------------------------------- crg = _CRG(platform, sys_clk_freq, x5_clk_freq) self.submodules.crg = crg # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = Cat(*[platform.request("user_led", i) for i in range(8)]), sys_clk_freq = sys_clk_freq) self.add_csr("leds") # Wishbone DMA Burst Testing # block of SRAM of WB dma testing self.add_ram("adc_sram", self.mem_map["adc_sram"], 8*4*4096) self.submodules.dma_burst = Wishbone_DMA_Burst() self.add_csr("dma_burst") self.add_wb_master(self.dma_burst.wishbone)
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", **kwargs): platform = ecp5_evn.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_main_ram_size=0x8000, **kwargs) # CRG -------------------------------------------------------------------------------------- crg = _CRG(platform, sys_clk_freq, x5_clk_freq) self.submodules.crg = crg # HyperRam --------------------------------------------------------------------------------- self.submodules.hyperram = HyperRAM(platform.request("hyperram")) self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus) self.add_memory_region("hyperram", self.mem_map["hyperram"], 8 * 1024 * 1024) # ADC -------------------------------------------------------------------------------------- trig_pad = platform.request("adc_trig", 0) self.submodules.adc = ADC3321_DMA(trig_pad) self.add_wb_master(self.adc.wishbone) self.add_csr("adc") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(8)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds") # Wishbone Debug # added io to platform, serial_wb self.submodules.bridge = UARTWishboneBridge(platform.request( "serial_wb", 1), sys_clk_freq, baudrate=115200) self.add_wb_master(self.bridge.wishbone) self.add_csr("analyzer") analyzer_signals = [ trig_pad, # self.adc.wishbone.stb, # self.adc.wishbone.dat_w, # self.adc.wishbone.ack, # self.adc.wishbone.adr, ] analyzer_depth = 256 # samples analyzer_clock_domain = "sys" self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, analyzer_depth, clock_domain=analyzer_clock_domain)
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", **kwargs): platform = ecp5_evn.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- crg = _CRG(platform, sys_clk_freq, x5_clk_freq) self.submodules.crg = crg
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="diamond", **kwargs): platform = ecp5_evn.Platform(toolchain=toolchain) SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, **kwargs) # crg crg = _CRG(platform, sys_clk_freq, x5_clk_freq) self.submodules.crg = crg
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", **kwargs): platform = ecp5_evn.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- crg = _CRG(platform, sys_clk_freq, x5_clk_freq) self.submodules.crg = crg # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(8)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", **kwargs): from litex.build.generic_platform import Subsignal, Pins, IOStandard platform = ecp5_evn.Platform(toolchain=toolchain) self._add_extentions(platform) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_main_ram_size=0x8000, **kwargs) # CRG -------------------------------------------------------------------------------------- crg = _CRG(platform, sys_clk_freq, x5_clk_freq) self.submodules.crg = crg # HyperRam --------------------------------------------------------------------------------- self.submodules.hyperram = HyperRAM(platform.request("hyperram")) #self.submodules.hyperram = HyperRAMX2(platform.request("hyperram")) self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus) self.add_memory_region("hyperram", self.mem_map["hyperram"], 8 * 1024 * 1024) # ADC RAM self.add_ram("adc_sram", self.mem_map["adc_sram"], 8 * 4 * 4096) # ADC -------------------------------------------------------------------------------------- adc_ctrl = platform.request("adc_ctrl", 0) adc_data = platform.request("adc_data", 0) self.add_csr("adc") self.submodules.adc = ADC3321_DMA(adc_ctrl, adc_data) self.add_wb_master(self.adc.wishbone) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(8)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds") # ADC SPI bus ------------------------------------------------------------------------------ # max SPI frequency is 20 MHz self.add_csr("adc_spi") self.submodules.adc_spi = SPIMaster(platform.request("adc_spi", 1), 24, sys_clk_freq, int(sys_clk_freq / 80), with_csr=True) # Wishbone Debug # added io to platform, serial_wb self.submodules.bridge = UARTWishboneBridge(platform.request( "serial_wb", 1), sys_clk_freq, baudrate=3000000) self.add_wb_master(self.bridge.wishbone) self.add_csr("analyzer") analyzer_signals = [ # self.adc.adc_frontend.adc_buffer.adc_dout0, # self.adc.adc_frontend.adc_buffer.adc_dout1, # self.adc.adc_frontend.adc_buffer.i_fclk, self.adc.adc_frontend_a.i_we, # self.adc.adc_frontend.i_re, # self.adc.adc_frontend.o_readable, # self.adc.adc_frontend.adc_buffer.o_dout, # self.adc.adc_frontend.adc_buffer.pulser.output, # self.adc.adc_frontend.adc_buffer.fifo.din, # self.adc.adc_frontend.o_dout, ] #t = Signal() #self.comb += [t.eq(clk_outputs.hr_p)] analyzer_depth = 512 # samples analyzer_clock_domain = "sys" self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, analyzer_depth, clock_domain=analyzer_clock_domain) # put pulser on pin.. debug_pins = platform.request("debug_pins") self.comb += debug_pins.dbg1.eq( self.adc.adc_frontend_a.adc_buffer.pulser.output)