def definition(io):
# XNOR for binary affine mapped multiplication
mul = mantle.NXOr(height=2, width=n)
m.wire(mul.I0, io.I0)
m.wire(mul.I1, io.I1)
pop = PopCount(n)
m.wire(mul.O, pop.I)
m.wire(pop.O, io.P)
width = log2(n)+2
sign = mantle.UGE(width)
m.wire(m.zext(pop.O, 1), sign.I0)
m.wire(m.bits(n, width), sign.I1)
m.wire(sign.O, io.O)
def definition(io):
load = io.LOAD
baud = rising(io.SCK) | falling(io.SCK)
valid_counter = mantle.CounterModM(buf_size, 12, has_ce=True)
m.wire(load & baud, valid_counter.CE)
valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)] # len = 32
valid = m.GND
for i in valid_list:
valid = valid | mantle.Decode(i, 12)(valid_counter.O)
# register on input
st_in = mantle.Register(width, has_ce=True)
st_in(io.DATA)
m.wire(load, st_in.CE)
# --------------------------DOWNSCALING----------------------------- #
# downscale the image from 352x288 to 32x32
Downscale = m.DeclareCircuit(
'Downscale',
"I_0_0", m.In(m.Array(1, m.Array(1, m.Array(width, m.Bit)))),
"WE", m.In(m.Bit), "CLK", m.In(m.Clock),
"O", m.Out(m.Array(width, m.Bit)), "V", m.Out(m.Bit))
dscale = Downscale()
m.wire(st_in.O, dscale.I_0_0[0][0])
m.wire(1, dscale.WE)
m.wire(load, dscale.CLK)
add16 = mantle.Add(width) # needed for Add16 definition
# --------------------------FILL IMG RAM--------------------------- #
# each valid output of dscale represents an entry of 32x32 binary image
# accumulate each group of 32 entries into a 32-bit value representing a row
col = mantle.CounterModM(32, 6, has_ce=True)
col_ce = rising(valid)
m.wire(col_ce, col.CE)
# shift each bit in one at a time until we get an entire row
px_bit = mantle.ULE(16)(dscale.O, m.uint(THRESH, 16)) & valid
row_reg = mantle.SIPO(32, has_ce=True)
row_reg(px_bit)
m.wire(col_ce, row_reg.CE)
# reverse the row bits since the image is flipped
row = reverse(row_reg.O)
rowaddr = mantle.Counter(6, has_ce=True)
img_full = mantle.SRFF(has_ce=True)
img_full(mantle.EQ(6)(rowaddr.O, m.bits(32, 6)), 0)
m.wire(falling(col.COUT), img_full.CE)
row_ce = rising(col.COUT) & ~img_full.O
m.wire(row_ce, rowaddr.CE)
waddr = rowaddr.O[:5]
rdy = col.COUT & ~img_full.O
pulse_count = mantle.Counter(2, has_ce=True)
we = mantle.UGE(2)(pulse_count.O, m.uint(1, 2))
pulse_count(CE=(we|rdy))
# ---------------------------UART OUTPUT----------------------------- #
row_load = row_ce
row_baud = mantle.FF()(baud)
uart_row = UART(32)
uart_row(CLK=io.CLK, BAUD=row_baud, DATA=row, LOAD=row_load)
uart_addr = UART(5)
uart_addr(CLK=io.CLK, BAUD=row_baud, DATA=waddr, LOAD=row_load)
m.wire(waddr, io.WADDR)
m.wire(img_full, io.DONE) #img_full
m.wire(uart_row, io.UART) #uart_st
m.wire(row, io.O)
m.wire(we, io.VALID)
m.wire(valid, io.T0)
m.wire(uart_addr, io.T1)
def definition(cam):
edge_f = falling(cam.SCK)
edge_r = rising(cam.SCK)
# ROM to store commands
rom_index = mantle.Counter(4, has_ce=True)
rom = ROM16(4, init, rom_index.O)
# Message length is 16 bits, setup counter to generate done signal
# after EOM
done_counter = mantle.Counter(5, has_ce=True, has_reset=True)
count = done_counter.O
done = mantle.Decode(16, 5)(count)
# State machine to generate run signal (enable)
run = mantle.DFF(has_ce=True)
run_n = mantle.LUT3([0, 0, 1, 0, 1, 0, 1, 0])
run_n(done, trigger, run)
run(run_n)
m.wire(edge_f, run.CE)
# Reset the message length counter after done
run_reset = mantle.LUT2(I0 | ~I1)(done, run)
done_counter(CE=edge_r, RESET=run_reset)
# State variables for high-level state machine
ready = mantle.LUT2(~I0 & I1)(run, edge_f)
start = mantle.ULE(4)(rom_index.O, m.uint(3, 4))
burst = mantle.UGE(4)(rom_index.O, m.uint(9, 4))
# Shift register to store 16-bit command|data to send
mosi = mantle.PISO(16, has_ce=True)
# SPI enable is negative of load-don't load and shift out data at the
# same time
enable = mantle.LUT3(I0 & ~I1 & ~I2)(trigger, run, burst)
mosi(~burst, rom.O, enable)
m.wire(edge_f, mosi.CE)
# Shit register to read in 8-bit data
miso = mantle.SIPO(8, has_ce=True)
miso(cam.MISO)
valid = mantle.LUT2(~I0 & I1)(enable, edge_r)
m.wire(valid, miso.CE)
# Capture done state variable
cap_done = mantle.SRFF(has_ce=True)
cap_done(mantle.EQ(8)(miso.O, m.bits(0x08, 8)), 0)
m.wire(enable & edge_r, cap_done.CE)
# Use state variables to determine what commands are sent (how)
increment = mantle.LUT4(I0 & (I1 | I2) & ~I3)(
ready, start, cap_done, burst)
m.wire(increment, rom_index.CE)
# wire outputs
m.wire(enable, cam.EN)
m.wire(mosi.O, cam.MOSI)
m.wire(miso.O, cam.DATA)
m.wire(burst, cam.VALID)
# --------------------------UART OUTPUT---------------------------- #
# run UART at 2x SPI rate to allow it to keep up
baud = edge_r | edge_f
# reset when SPI burst read (image transfer) begins
ff = mantle.FF(has_ce=True)
m.wire(edge_r, ff.CE)
u_reset = mantle.LUT2(I0 & ~I1)(burst, ff(burst))
# UART data out every 8 bits
u_counter = mantle.CounterModM(8, 3, has_ce=True, has_reset=True)
u_counter(CE=edge_r, RESET=u_reset)
load = burst & rising(u_counter.COUT)
uart = UART(8)
uart(CLK=cam.CLK, BAUD=baud, DATA=miso, LOAD=load)
# wire output
m.wire(uart, cam.UART)
# generate signal for when transfer is done
data_count = mantle.Counter(18, has_ce=True)
tx_done = mantle.SRFF(has_ce=True)
# transfer has size 153600 bytes, first 2 bytes are ignored
tx_done(mantle.EQ(18)(data_count.O, m.bits(153602, 18)), 0)
m.wire(load, tx_done.CE)
m.wire(load, data_count.CE)
# wire output
m.wire(tx_done, cam.DONE)
def definition(io):
load = io.LOAD
baud = rising(io.SCK) | falling(io.SCK)
valid_counter = mantle.CounterModM(buf_size, 13, has_ce=True)
m.wire(load & baud, valid_counter.CE)
valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)]
valid = m.GND
for i in valid_list:
valid = valid | mantle.Decode(i, 13)(valid_counter.O)
# register on input
st_in = mantle.Register(16, has_ce=True)
st_in(io.DATA)
m.wire(load, st_in.CE)
# --------------------------DOWNSCALING----------------------------- #
# downscale the image from 320x240 to 16x16
Downscale = m.DeclareCircuit(
'Downscale',
"I_0_0", m.In(m.Array(1, m.Array(1, m.Array(16, m.Bit)))),
"WE", m.In(m.Bit), "CLK", m.In(m.Clock),
"O", m.Out(m.Array(16, m.Bit)), "V", m.Out(m.Bit))
dscale = Downscale()
m.wire(st_in.O, dscale.I_0_0[0][0])
m.wire(1, dscale.WE)
m.wire(load, dscale.CLK)
add16 = mantle.Add(16) # needed for Add16 definition
# --------------------------FILL IMG RAM--------------------------- #
# each valid output of dscale represents a pixel in 16x16 binary image
# accumulate each group of 16 pixels into a 16-bit value representing
# a row in the image
col = mantle.CounterModM(16, 5, has_ce=True)
col_ce = rising(valid)
m.wire(col_ce, col.CE)
# shift each bit in one at a time until we get an entire row
px_bit = mantle.ULE(16)(dscale.O, m.uint(THRESH, 16)) & valid
row_reg = mantle.SIPO(16, has_ce=True)
row_reg(px_bit)
m.wire(col_ce, row_reg.CE)
# reverse the row bits since the image is flipped
row = reverse(row_reg.O)
rowaddr = mantle.Counter(5, has_ce=True)
img_full = mantle.SRFF(has_ce=True)
img_full(mantle.EQ(5)(rowaddr.O, m.bits(16, 5)), 0)
m.wire(falling(col.COUT), img_full.CE)
row_ce = rising(col.COUT) & ~img_full.O
m.wire(row_ce, rowaddr.CE)
waddr = rowaddr.O[:4]
# we_counter = mantle.CounterModM(16, 5, has_ce=True)
# m.wire(rising(valid), we_counter.CE)
rdy = col.COUT & ~img_full.O
pulse_count = mantle.Counter(5, has_ce=True)
we = mantle.UGE(5)(pulse_count.O, m.uint(1, 5))
pulse_count(CE=(we | rdy))
# ---------------------------UART OUTPUT----------------------------- #
row_load = row_ce
row_baud = mantle.FF()(baud)
uart_row = UART(16)
uart_row(CLK=io.CLK, BAUD=row_baud, DATA=row, LOAD=row_load)
uart_addr = UART(4)
uart_addr(CLK=io.CLK, BAUD=row_baud, DATA=waddr, LOAD=row_load)
# split 16-bit row data into 8-bit packets so it can be parsed
low_byte = row & LOW_MASK
high_byte = row & HIGH_MASK
uart_counter = mantle.CounterModM(8, 4, has_ce=True)
m.wire(rising(valid), uart_counter.CE)
m.wire(waddr, io.WADDR)
m.wire(img_full, io.DONE)
m.wire(uart_row, io.UART)
m.wire(row, io.O)
m.wire(we, io.VALID)