示例#1
0
def stepperdriver(dir_pino, step_pino, en_pino, clock,
                  reset, xula_freq=12e6):

    counter_photodiode = Signal(intbv(0, min=0, max=round(12e6)))
    
    @always_comb
    def dirpin():
        if reset == 0:
            dir_pino.next = 1
            en_pino.next = 1
        else:
            dir_pino.next = 0
            en_pino.next = 0

    @always_seq(clock.posedge, reset)
    def count():
        if counter_photodiode >= counter_photodiode.max-1:
            counter_photodiode.next = 0
            step_pino.next = not step_pino
        else:
            counter_photodiode.next = counter_photodiode+1
    return instances() 


    return instances()
def PolarOdometers(left_count, left_speed, right_count, right_speed,
                   angle_count, angle_speed, distance_count, distance_speed):
    """

    Virtual angle and distance odometers

    Convert differential drive odometer counts and speeds (left, right) to
    polar odometers counts and speeds (angle, distance).

    left_count, left_speed

        Input count and speed of the left odometer.

    right_count, right_speed

        Input count and speed of the left odometer.

    angle_count, angle_speed

        Output count and speed of the virtual angle odometer.

    distance_count, distance_speed

        Output count and speed of the virtual distance odometer.

    """

    count_converter = LeftRightToAngleDistance(left_count, right_count,
                                               angle_count, distance_count)

    speed_converter = LeftRightToAngleDistance(left_speed, right_speed,
                                               angle_speed, distance_speed)

    return instances()
示例#3
0
文件: led_count.py 项目: wingel/rhea
def led_count(clock, reset, leds, led_rate=333e-3):
    """LED count
    Increment a counter at a rate that is visible on a
    bank of LEDs.

    Arguments:
        clock: system clock
        reset: system reset
        leds (Signal(intbv)): LED bits

    myhdl convertible
    """
    cnt_max = int(clock.frequency * led_rate)
    clk_cnt = Signal(intbv(1, min=0, max=cnt_max))
    rled = Signal(modbv(0)[len(leds):])

    # assign the port LED to the internal register led
    assign(leds, rled)

    # @todo: create a module to select a rate strobe,
    #    the module will return a signal that is from
    #    an existing rate or a generator and signal
    @always_seq(clock.posedge, reset=reset)
    def beh():
        if clk_cnt == 0:
            rled.next = rled + 1
        clk_cnt.next = clk_cnt + 1

    return myhdl.instances()
示例#4
0
def Test():
    # IEEE754 Single
    EXPONENT_WIDTH = 8
    FRACTION_WIDTH = 23
    EXPONENT_BIAS = 127
    
    INT_WIDTH = 6
    
    float_sig = Signal(modbv(0)[(1+EXPONENT_WIDTH+FRACTION_WIDTH):])
    int_sig = Signal(modbv(0)[INT_WIDTH:])
    
    convertor = IntToFloat(
            float_sig,
            int_sig,
            exponent_width=EXPONENT_WIDTH,
            fraction_width=FRACTION_WIDTH,
            exponent_bias=EXPONENT_BIAS)
    
    @instance
    def stimulus():
        print('input', 'output', sep='\t')
        for k in range(-2**(INT_WIDTH-1), 2**(INT_WIDTH-1)):
            int_sig.next = k
            yield delay(10)
            int_val = int(int_sig)
            if k < 0:
                int_val = ~int_val + 1
                int_val &= 2**INT_WIDTH - 1
                int_val = -int_val
            print(int_val, uint_to_float(int(float_sig))[0], sep='\t')
            
    return instances()
示例#5
0
  def block_atomic_oper(self, pars, reset, clk, cmd, stage_iA, stage_iB, stage_o):
    """ Atomic Command block """

    @always(clk.posedge)
    def atomic_operation_assign_process():
      if ( cmd == 0x31):     # A+B
        stage_o.data.next = stage_iA.data + stage_iB.data
      elif ( cmd == 0x32):   # A-B
        stage_o.data.next = stage_iA.data - stage_iB.data
      elif ( cmd == 0x33):  # B-A
        stage_o.data.next = stage_iB.data - stage_iA.data
      elif ( cmd == 0x34):  # A*B
        stage_o.data.next = stage_iA.data * stage_iB.data
      elif ( cmd == 0x00):   # No Operation
        stage_o.data.next = stage_o.data

      if (stage_iA.valid == 1 and stage_iB.valid == 1):
          stage_o.valid.next = 1
      else:
          stage_o.valid.next = 0

      if (stage_iA.sop == 1 and stage_iB.sop == 1):
          stage_o.sop.next = 1
      else:
          stage_o.sop.next = 0

      if (stage_iA.eop == 1 and stage_iB.eop == 1):
          stage_o.eop.next = 1
      else:
          stage_o.eop.next = 0

    return instances()
示例#6
0
def des(
        # ~~~[Ports]~~~
        clock,  #
        rx,  #
        bit_in,  #
        enable,  #
        # ~~~[Parameters]~~~
    size=8):
    assert len(rx) == size
    # serialization register
    ser_reg = Signal(intbv(0)[size:])
    bitcnt = Signal(intbv(size - 1, min=0, max=size + 1))

    @always(clock.posedge)
    def deserialization():
        if (enable == 1):

            if bitcnt == (size - 1):
                rx.next = ((ser_reg << 1) | bit_in) & 0xFF
                bitcnt.next = 0
            else:
                ser_reg.next = ((ser_reg << 1) | bit_in) & 0xFF
                bitcnt.next = bitcnt + 1
        else:
            ser_reg.next = 0
            rx.next = 0
            bitcnt.next = size - 1

    return myhdl.instances()
示例#7
0
def procuder_consumer(clock_write, clock_read, fbus, start):
    # FIFO writer and reader
    _wr = Signal(bool(0))
    w = len(fbus.write_data)

    @instance
    def tb_always_wr():
        was_full = False
        wrd = modbv(0)[w:]
        while True:
            if start:
                break
            yield clock_write.posedge

        while True:
            yield clock_write.posedge
            if not fbus.full and was_full:
                was_full = False
                for _ in range(17):
                    yield clock_write.posedge
            elif not fbus.full:
                fbus.write_data.next = wrd
                _wr.next = True
                yield delay(1)
                if not fbus.full:
                    wrd[:] += 1
            else:
                _wr.next = False
                was_full = True

    @always_comb
    def tb_always_wr_gate():
        fbus.write.next = _wr and not fbus.full

    @instance
    def tb_always_rd():
        rdd = modbv(0)[w:]
        while True:
            if start:
                break
            yield clock_write.posedge

        while True:
            try:
                yield clock_read.posedge
                if not fbus.empty:
                    fbus.read.next = True
                else:
                    fbus.read.next = False

                if fbus.read_valid:
                    tmp = fbus.read_data
                    assert tmp == rdd, " %d != %d " % (tmp, rdd)
                    rdd[:] += 1
            except AssertionError as err:
                for _ in range(10):
                    yield clock_read.posedge
                raise err

    return myhdl.instances()
示例#8
0
def testBench():

    signal_1bit = [Signal(intbv(0)[1:]) for i in range(7)]
    RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch = signal_1bit
    ALUop = Signal(intbv(0)[2:])

    opcode = Signal(intbv(0)[6:])

    control_inst = toVHDL(control, opcode, RegDst, Branch, MemRead, MemtoReg,
                          ALUop, MemWrite, ALUSrc, RegWrite)

    @instance
    def stimulus():
        for op_value in [
                0, int('100011', 2),
                int('101011', 2),
                int('000100', 2)
        ]:
            opcode.next = op_value
            yield delay(10)

            print 'opcode: ', bin(opcode, 6)
            print RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, bin(
                ALUop, 2)

    return instances()
示例#9
0
文件: stack.py 项目: xialulee/WaveSyn
def Stack(dout, din, full, empty, push, clk, posedge=True, width=8, depth=128):
    mem = [Signal(intbv(0)[width:]) for i in range(depth)]
    pointer = Signal(modbv(0, min=0, max=depth))
    
    if posedge:
        edge = clk.posedge
    else:
        edge = clk.negedge

    @always_seq(edge, reset=None)
    def operate():
        if push:
            if pointer == depth - 1:
                full.next = True
                empty.next = False
            if not full:
                mem[pointer].next = din
                pointer.next = pointer + 1                
        else:
            if pointer == 1:
                empty.next = True
                full.next = False
            if not empty:
                dout.next = mem[pointer-1]
                pointer.next = pointer - 1

    return instances()
示例#10
0
文件: alu.py 项目: bigeagle/pymips
def testBench_alu():

    control_i = Signal(intbv(0)[4:])

    op1_i = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))
    op2_i = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))

    out_i = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))

    zero_i = Signal(bool(False))

    alu_i = ALU(control_i, op1_i, op2_i, out_i, zero_i)
    #alu_i = toVHDL(ALU, control_i, op1_i, op2_i, out_i, zero_i)
    #alu_i = analyze(alu, control_i, op1_i, op2_i, out_i, zero_i)

    control_func = (('0000', 'AND'), ('0001', 'OR'), ('0010', 'add'), ('0110', 'substract'), ('0111', '<'), ('1100', 'NOR'))

    @instance
    def stimulus():
        for control_val, func in [(int(b, 2), func) for (b, func) in control_func]:
            control_i.next = Signal(intbv(control_val))

            op1_i.next, op2_i.next = [intbv(random.randint(0, 255))[32:] for i in range(2)]

            yield delay(10)
            print "Control: %s | %i %s %i | %i | z=%i" % (bin(control_i, 4), op1_i, func, op2_i, out_i, zero_i)

    return instances()
示例#11
0
文件: icestick.py 项目: gbin/rhea
def icestick(clock, led, pmod, uart_tx, uart_rx):
    """ Lattice Icestick example
    """
    
    glbl = Global(clock, None)    
    gticks = glbl_timer_ticks(glbl, include_seconds=True)

    # get interfaces to the UART fifos
    fbustx = FIFOBus(width=8, size=8)
    fbusrx = FIFOBus(width=8, size=8)

    # get the UART comm from PC
    guart = uartlite(glbl, fbustx, fbusrx, uart_tx, uart_rx)

    @always_comb
    def beh_loopback():
        fbusrx.rd.next = not fbusrx.empty
        fbustx.wr.next = not fbusrx.empty
        fbustx.wdata.next = fbusrx.rdata

    lcnt = Signal(modbv(0, min=0, max=4))
    @always(clock.posedge)
    def beh_led_count():
        if glbl.tick_sec:
            lcnt.next = lcnt + 1;
        led.next = (1 << lcnt)

    # system to test/interface
    
    # other stuff

    return instances()
def test_video_interface():

    # resolution of the video is kept low to reduce simulation time
    res = (50, 50)

    # a sample pixel
    pixel = [1, 0, 0]

    clock = Signal(bool(0))
    clock_drive = clock_driver(clock)

    video_interface = VideoInterface(clock, res)

    @instance
    def test():

        video_interface.reset_cursor()
        yield video_interface.enable_video()

        # iterating over the frame
        for _ in range(res[0]*res[1]):
            # Sending a pixel
            yield video_interface.write_pixel(pixel), \
                video_interface.read_pixel()
            assert video_interface.get_pixel() == pixel

        yield video_interface.disable_video()

    return instances()
示例#13
0
def IntToFloat(
        float_output,
        int_input,
        exponent_width,
        fraction_width,
        exponent_bias):
    INT_WIDTH = len(int_input)
    FLOAT_WIDTH = len(float_output)
    
    sign = Signal(bool(0))
    sign_getter = SignGetter(sign, int_input)
    
    abs_int = Signal(modbv(0)[INT_WIDTH:])           
    abs_calculator = Abs(abs_int, int_input)
    
    abs_float = Signal(modbv(0)[(1+exponent_width+fraction_width):])         
    float_calculator = UIntToFloat(
            abs_float, abs_int, 
            exponent_width, fraction_width, exponent_bias)
    
    signed_float = ConcatSignal(sign, abs_float(FLOAT_WIDTH-1, 0))
    
    @always_comb
    def make_output():
        float_output.next = signed_float
        
    return instances()
示例#14
0
def UIntToFloat(
        float_output,
        uint_input,
        exponent_width,
        fraction_width,
        exponent_bias
    ):
    
    # Calculating unbiased and biased exponent.
    unbiased_exponent = Signal(modbv(0)[exponent_width:])
    biased_exponent = Signal(modbv(0)[exponent_width:])
    nz_flag = Signal(bool(0))
    unbiased_exponent_calculator = PriorityEncoder(
            unbiased_exponent, nz_flag, uint_input)
    @always_comb
    def biased_exponent_calculator():
        biased_exponent.next = unbiased_exponent + exponent_bias
    
    # Calculating fraction part. 
    fraction = Signal(modbv(0)[fraction_width:])
    fraction_calculator = UIntToFraction(
            fraction, uint_input, unbiased_exponent)
    
    float_sig = ConcatSignal(bool(0), biased_exponent, fraction)
    
    @always_comb
    def make_output():
        if uint_input == 0:
            float_output.next = 0
        else:
            float_output.next = float_sig
        
            
    return instances()
示例#15
0
    def gen(self):
        system = self.system
        bus = self.bus()

        mem = [ Signal(intbv(0)[self.accumulator_width:])
                for _ in range(1<<self.sample_width) ]

        inc = Signal(False)
        inc_idx = Signal(intbv(0)[self.sample_width:])
        inc_val = Signal(intbv(0)[self.accumulator_width:])

        @always_seq(system.CLK.posedge, system.RST)
        def contributions_inst():
            bus.RD_DATA.next = 0

            if bus.WR:
                mem[bus.ADDR].next = bus.WR_DATA
            elif inc:
                inc.next = 0
                mem[inc_idx].next = inc_val

            if bus.RD:
                bus.RD_DATA.next = mem[bus.ADDR]
            elif self.STROBE:
                inc.next = 1
                inc_idx.next = self.SAMPLE
                inc_val.next = mem[self.SAMPLE].next + 1

        return instances()
def cezar(clk, reset, y, x):
    state_t = enum('enc', 'dec')
    accumulator = Signal(intbv(0)[32:])
    counter = Signal(intbv(0)[32:])
    state = Signal(state_t.COUNT)
    message = Signal(intbv(0)[4:])
    key = Signal(intbv(0)[3:].signed())

    @always_seq(clk.posedge, reset=reset)
    def enc_proc():
        if state == state_t.dec:
            key.next = -key

        x.next = message + key
        if x > 15:
            x.next = 0 + key
        elif x < 0:
            x.next = 15 + key

        elif state == state_t.enc:
            key.next = key
            x.next = message + key
            if x > 15:
                x.next = 0 + key
            elif x < 0:
                x.next = 15 + key

        else:
            raise ValueError("Undefined state")

    return instances()
示例#17
0
def Test():
    depth = 4
    width = 4
    
    dout = Signal(modbv(0)[width:])
    din = Signal(modbv(0)[width:])
    full = Signal(bool(0))
    empty = Signal(bool(0))
    push = Signal(bool(0))
    clk = Signal(bool(0))
    
    stack = Stack(dout, din, full, empty, push, clk, width=width, depth=depth)
    
    @instance
    def stimulus():
        print('dout\tdin\tfull\tempty\tpush')
        push.next = 1
        for k in range(16):
            din.next = k + 1
            push.next = k < 8
            yield delay(10)
            clk.next = 1
            yield delay(10)
            clk.next = 0
            print(dout, din, full, empty, push, sep='\t')
            
    return instances()
示例#18
0
def depp(clock,a_dstb,a_astb,a_write,a_wait,a_addr_reg,a_db,to_rpi2B):

    @always_comb
    def rtl1():
        a_wait.next = not a_astb or not a_dstb

    @always(clock.posedge)
    def rtl2():
        a_astb_sr.next = concat(a_astb_sr[2:0], a_astb)
        a_dstb_sr.next = concat(a_dstb_sr[2:0], a_dstb)

    @always(clock.posedge)
    def rtl3():
        if (~a_write and a_astb_sr == 4):
            a_addr_reg.next = a_db

    @always(clock.posedge)
    def rtl4():
        if (~a_write and a_dstb_sr == 4):
            a_data_reg.next = a_db

    @always_comb
    def rtl5():
	if(a_write == 1):
            to_rpi2B.next = a_data_reg

    return myhdl.instances()
示例#19
0
def ShiftBuf(buf, bitin, clk, posedge=True, width=4, direction='right'):
    if posedge:
        edge = clk.posedge
    else:
        edge = clk.negedge

    if width < 1:
        raise ValueError('width should larger than 0.')

    buf = [Signal(bool(0)) for i in range(width)]

    if direction.lower() in ('right', 'r'):

        @always_seq(edge, reset=None)
        def do():
            for i in range(0, width - 1):
                buf[i].next = buf[i + 1]
            buf[width - 1].next = bitin
    elif direction.lower() in ('left', 'l'):

        @always_seq(edge, reset=None)
        def do():
            for i in range(1, width):
                buf[i].next = buf[i - 1]
            buf[0].next = bitin

    return instances()
示例#20
0
文件: dpram.py 项目: wingel/sds7102
    def gen(self):
        system0 = self.system0
        bus0 = self.bus0()

        ram = [ Signal(intbv(0)[self.data_width:])
                for _ in range(self.addr_depth) ]

        @always_seq(system0.CLK.posedge, system0.RST)
        def seq0():
            if bus0.WR:
                ram[bus0.ADDR].next = bus0.WR_DATA

            if bus0.RD and bus0.ADDR < len(ram):
                bus0.RD_DATA.next = ram[bus0.ADDR]
            else:
                bus0.RD_DATA.next = 0

        system1 = self.system1
        bus1 = self.bus1()

        @always_seq(system1.CLK.posedge, system1.RST)
        def seq1():
            if bus1.WR:
                ram[bus1.ADDR].next = bus1.WR_DATA

            if bus1.RD and bus1.ADDR < len(ram):
                bus1.RD_DATA.next = ram[bus1.ADDR]
            else:
                bus1.RD_DATA.next = 0

        return instances()
示例#21
0
def TestBench(steps, *args):
    # useful values
    # clock
    clk = Signal(bool(0))
    clkDriver = ClkDriver(clk=clk,
                          period=2)

    # counter
    cnt = Signal(intbv(0, min=0, max=steps+2))
    counter = Counter(clk=clk,
                      cnt=cnt)

    # Template
    template = Template(clk=clk)

    # debugger
    debugger = Debugger(period=1,
                        funcs={"cnt":lambda c: str(int(c)),
                               "clk":lambda c: str(int(c)),
                              },
                        cnt=cnt,
                        clk=clk,
                       )

    @instance
    def tests():
        for i in range(steps):
            yield delay(1)

    return instances()
示例#22
0
def ser(
        # ~~~[Ports]~~~
        clock,  #
        tx,  #
        bit_out,  #
        # ~~~[Parameters]~~~
    enable,
        size=8):
    assert len(tx) == size
    # serialization regiester
    ser_reg = Signal(intbv(0)[size:])
    bitcnt = Signal(intbv(size - 1, min=0, max=size + 1))

    @always(clock.posedge)
    def serialization():
        if (enable == 1):
            if bitcnt == (size - 1):
                bitcnt.next = 0
                ser_reg.next = (tx << 1) & 0xFF
                bit_out.next = tx[7]
            else:
                bit_out.next = ser_reg[7]
                ser_reg.next = (ser_reg << 1) & 0xFF
                bitcnt.next = bitcnt + 1
        else:
            ser_reg.next = 0
            bitcnt.next = size - 1
            bit_out.next = 0

    return myhdl.instances()
示例#23
0
    def gen(self):
        system0 = self.system0
        bus0 = self.bus0()

        ram = [
            Signal(intbv(0)[self.data_width:]) for _ in range(self.addr_depth)
        ]

        @always_seq(system0.CLK.posedge, system0.RST)
        def seq0():
            if bus0.WR:
                ram[bus0.ADDR].next = bus0.WR_DATA

            if bus0.RD and bus0.ADDR < len(ram):
                bus0.RD_DATA.next = ram[bus0.ADDR]
            else:
                bus0.RD_DATA.next = 0

        system1 = self.system1
        bus1 = self.bus1()

        @always_seq(system1.CLK.posedge, system1.RST)
        def seq1():
            if bus1.WR:
                ram[bus1.ADDR].next = bus1.WR_DATA

            if bus1.RD and bus1.ADDR < len(ram):
                bus1.RD_DATA.next = ram[bus1.ADDR]
            else:
                bus1.RD_DATA.next = 0

        return instances()
示例#24
0
def xula_vga(
    # ~~~[PORTS]~~~
    vselect,
    hsync, vsync, 
    red, green, blue,
    pxlen, active,
    clock,
    reset=None,

    # ~~~~[PARAMETERS]~~~~
    # @todo: replace these parameters with a single VGATimingParameter
    resolution=(640, 480,),
    color_depth=(8, 8, 8,),
    refresh_rate=60,
    line_rate=31250
):
    """
    (arguments == ports)
    Arguments:
        vselect:

    Parameters:
        resolution: the video resolution
        color_depth: the color depth of a pixel, the number of bits
            for each color component in a pixel.
        refresh_rate: the refresh rate of the video
    """
    # stub out reset if needed
    if reset is None:
        reset = ResetSignal(0, active=0, async=False)

        @always(clock.posedge)
        def reset_stub():
            reset.next = not reset.active

    else:
        reset_stub = None

    # create the system-level signals, overwrite clock, reset
    glbl = Global(clock=clock, reset=reset)

    # VGA inteface
    vga = VGA()
    # assign the top-level ports to the VGA interface
    vga.assign(
        hsync=hsync, vsync=vsync,
        red=red, green=green, blue=blue,
        pxlen=pxlen, active=active
    )

    # video memory interface
    vmem = VideoMemory(color_depth=color_depth)
        
    # color bar generation
    bar_inst = color_bars(glbl, vmem, resolution=resolution)

    # VGA driver
    vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution)

    return myhdl.instances()
示例#25
0
def toplevel(i_clk, i_rpi2B,fr_depp,o_rpi2B,to_depp):
    dut_rpi2B_io = rpi2B_io(i_rpi2B,o_depp,o_rpi2B,to_depp)
    reset_dly_cnt = Signal(intbv(0)[5:])
    @always(i_clk.posedge)
    def reset_tst():
        '''
        For the first 4 clocks the reset is forced to lo
        for clock 6 to 31 the reset is set hi
        then the reset is lo
        '''
        if (reset_dly_cnt < 31):
            reset_dly_cnt.next = reset_dly_cnt + 1
            if (reset_dly_cnt <= 4):
                reset.next = 0
            if (reset_dly_cnt >= 5):
                reset.next = 1
                #i_int.next = 1
        else:
            reset.next = 0
 
    

    dut_my_wbdepp = my_wbdepp(i_clk,i_astb_n,i_dstb_n,i_write_n,to_depp,\
    fr_depp,o_wait,o_wb_cyc,o_wb_stb, \
    o_wb_we,o_wb_addr,o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,i_int)
      
    return myhdl.instances()
示例#26
0
def sigmoid(t_clk, t_reset, t_y_out, t_x, t_prec=4, fraction=16):
    """

    :param x:
    :param prec:
    :return:
    """
    const_1 = Signal(intbv(65536)[32:])
    state_t = enum('count', 'result')
    state = Signal(state_t.count)
    accumulator = Signal(intbv(0)[32:])
    counter = Signal(intbv(0)[32:])
    t_exp_out, t_exp_end = [Signal(intbv(0)[32:]) for i in range(2)]
    t_exp_start = Signal(intbv(1)[32:])
    exponential_1 = exponential(t_clk, t_reset, t_exp_out, t_x.tdata, t_exp_end, t_exp_start, t_prec, fraction)

    @always_seq(t_clk.posedge, reset=t_reset)
    def sigmoids():
        """

        :return:
        """
        if state == state_t.count:
            if t_exp_end == 1:
                t_exp_start.next = 0
                accumulator.next = ((t_exp_out << fraction) // (t_exp_out + const_1))
                state.next = state_t.result
        elif state == state_t.result:
            t_exp_start.next = 1
            t_y_out.tdata.next = accumulator
            state.next = state_t.count
        else:
            raise ValueError("Undefined state")

    return instances()
示例#27
0
def testBench():

    i_in, pc_in, i_out, pc_out = [Signal(intbv(0)[32:]) for i in range(4)]

    clk, rst, stall = [Signal(intbv(0)[1:]) for i in range(3)]

    latch_inst = toVHDL(latch_if_id, clk, rst, i_in, pc_in, i_out, pc_out, stall)

    @instance
    def stimulus():
        for i in range(10):
            i_in.next, pc_in.next = [Signal(intbv(random.randint(0, 255))[32:]) for i in range(2)]

            if random.random() > 0.10:
                clk.next = 1
            if random.random() > 0.75:
                rst.next = 1
            if random.random() > 0.5:
                stall.next = 1

            yield delay(1)
            print "Inputs: %i %i | clk: %i  rst: %i stall:%i | Output: %i %i" % (i_in, pc_in, clk, rst, stall, i_out, pc_out)
            clk.next = 0
            rst.next = 0
            stall.next = 0
            yield delay(1)

    return instances()
示例#28
0
def tag_ram_instance(data_in,data_out,we,adr,clock,reset,config):
    """
    data_in: TagDataBundle
    data_out: TagDataBundle
    we: Write enable signal
    adr: RAM address to read/write from/to
    clock, reset
    config: CacheConfig
    """

    width = data_in.get_len()

    ram_array = [Signal(modbv(0)[width:]) for ii in range(0, config.tag_ram_size)]

    tagdata_in = Signal(modbv(0)[width:])
    tagdata_out = Signal(modbv(0)[width:])

    tagdi_instance = data_in.to_bit_vector(tagdata_in)
    tagdo_instance = data_out.from_bit_vector(tagdata_out)

    @always(clock.posedge)
    def ram_seq():
       
        if reset: # explicit reset handling here
            tagdata_out.next = 0
        if we:
            ram_array[adr].next = tagdata_in
            tagdata_out.next = tagdata_in # write first ram
        else:
            tagdata_out.next = ram_array[adr]

    return instances()
示例#29
0
文件: alu.py 项目: bigeagle/pymips
def testBench_alu():

    control_i = Signal(intbv(0)[4:])

    op1_i = Signal(intbv(0, min=-(2**31), max=2**31 - 1))
    op2_i = Signal(intbv(0, min=-(2**31), max=2**31 - 1))

    out_i = Signal(intbv(0, min=-(2**31), max=2**31 - 1))

    zero_i = Signal(bool(False))

    alu_i = ALU(control_i, op1_i, op2_i, out_i, zero_i)
    #alu_i = toVHDL(ALU, control_i, op1_i, op2_i, out_i, zero_i)
    #alu_i = analyze(alu, control_i, op1_i, op2_i, out_i, zero_i)

    control_func = (('0000', 'AND'), ('0001', 'OR'), ('0010', 'add'),
                    ('0110', 'substract'), ('0111', '<'), ('1100', 'NOR'))

    @instance
    def stimulus():
        for control_val, func in [(int(b, 2), func)
                                  for (b, func) in control_func]:
            control_i.next = Signal(intbv(control_val))

            op1_i.next, op2_i.next = [
                intbv(random.randint(0, 255))[32:] for i in range(2)
            ]

            yield delay(10)
            print "Control: %s | %i %s %i | %i | z=%i" % (bin(
                control_i, 4), op1_i, func, op2_i, out_i, zero_i)

    return instances()
示例#30
0
def test_spi_led(clock, sck, mosi, miso, cs, leds,out):
    clkdrv = ClkDriver(clock,period=10)
    ssled = spi_slave_led(clock, sck, mosi, miso, cs, leds,out)
    ts = ser (clock, tx, mosi, enable)

    @always_comb
    def map():
        sck.next = clock


    @instance
    def tbstim():
        yield delay(15)
        enable.next=1
        tx.next=42
        cs.next=0
        yield delay(90)
        enable.next=0
        cs.next=1
        #assert rx == 42

        yield delay(15)
        enable.next=1
        tx.next=98
        yield delay(70)
        tx.next=23
        yield delay(20)
        #assert rx == 98
        yield delay(90)
        #assert rx == 23
        enable.next=0
        yield delay(100)


    return myhdl.instances()
示例#31
0
文件: dummy.py 项目: wingel/sds7102
    def gen_internal(self):
        self.cur_count = Signal(intbv(0, 0, self.count + 1))
        self.cur_skip = Signal(intbv(0, 0, self.skip + 1))

        self.new_count = Signal(intbv(0, 0, self.count + 1))
        self.new_skip = Signal(intbv(0, 0, self.skip + 1))

        @always_comb
        def comb():
            self.new_count.next = self.cur_count
            self.new_skip.next = self.cur_skip

            if self.cur_skip != 0:
                self.new_skip.next = self.cur_skip - 1

            elif self.cur_count != self.count:
                if self.strobe:
                    self.new_count.next = self.cur_count + 1
                    self.new_skip.next = self.skip

        @always_seq(self.clk.posedge, self.rst)
        def seq():
            self.cur_count.next = self.new_count
            self.cur_skip.next = self.new_skip

        @always_comb
        def busy_comb():
            self.busy.next = 1
            if self.new_count != self.count and self.new_skip == 0:
                self.busy.next = 0

        return instances()
示例#32
0
def ProgramROM(
        data,
        addr):
    @always_comb
    def do():
        data.next = test_program[addr]
    return instances()
示例#33
0
文件: led_dance.py 项目: FelixVi/rhea
def led_dance(clock, reset, leds, led_rate=33e-3):
    """An interesting LED pattern

    Arguments:
        clock: system clock
        reset: system reset
        leds: LED bits

    Parameters:
        led_rate: the rate to blink, in seconds
    """
    cnt_max = int(clock.frequency * led_rate)
    clk_cnt = Signal(intbv(1, min=0, max=cnt_max))
    rled = Signal(modbv(0)[len(leds):])

    # assign the port LED to the internal register led
    assign(leds, rled)

    # @todo: create a module to select a rate strobe,
    #    the module will return a signal that is from
    #    an existing rate or a generator and signal
    mb = len(leds)-1
    d = modbv(0)[len(leds):]

    @always_seq(clock.posedge, reset=reset)
    def beh():
        if clk_cnt == 0:
            d[:] = (rled ^ 0x81) << 1
            rled.next = concat(d, rled[mb])
        clk_cnt.next = clk_cnt + 1

    return myhdl.instances()
示例#34
0
文件: icestick.py 项目: FelixVi/rhea
def icestick(clock, led, pmod, uart_tx, uart_rx):
    """ Lattice Icestick example
    """
    
    glbl = Global(clock, None)    
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # get interfaces to the UART fifos
    fbusrtx = FIFOBus(width=8)

    # get the UART comm from PC
    uart_inst = uartlite(glbl, fbusrtx, uart_tx, uart_rx)

    @always_comb
    def beh_loopback():
        fbusrtx.write_data.next = fbusrtx.read_data
        fbusrtx.write.next = (not fbusrtx.full) & fbusrtx.read

    lcnt = Signal(modbv(0, min=0, max=4))

    @always(clock.posedge)
    def beh_led_count():
        if glbl.tick_sec:
            lcnt.next = lcnt + 1;
        led.next = (1 << lcnt)

    # system to test/interface
    
    # other stuff

    return myhdl.instances()
示例#35
0
def Register(out, data, clk, en):

    """ Parallel load register
    
    out -- output bit vector
    data -- input bit vector
    clk -- clock signal
    en -- enable signal to send data to outputs
    
    """
    
    n = len(data)
    dff_inst = [None for i in range(n)]
    mux_inst = [None for i in range(n)]
    out_temp = [Signal(int(out(i))) for i in range(n)]
    out_list = [out(i) for i in range(n)]
    data_list = [data(i) for i in range(n)]
    input = [Signal(0) for i in range(n)]
    
    for i in range(n):
        mux_inst[i] = Mux21(input[i], en, out_list[i], data_list[i])
        dff_inst[i] = dff(out_temp[i], input[i], clk)
        
    @always_comb
    def connect_out_bits():
        for i in range(n):
            out.next[i] = out_temp[i]
        
    return instances()
示例#36
0
def para_rpi2B( clock, to_rpi2B,fr_rpi2B,a_dstb,a_astb,a_write,a_wait):
 
    reset_dly_cnt = Signal(intbv(0)[5:])
    @always( clock.posedge)
    def reset_tst():
        '''
        For the first 4 clocks the reset is forced to lo
        for clock 6 to 31 the reset is set hi
        then the reset is lo
        '''
        if (reset_dly_cnt < 10):
            reset_dly_cnt.next = reset_dly_cnt + 1
            if (reset_dly_cnt <= 4):
                reset.next = 0
            if (reset_dly_cnt >= 5):
                reset.next = 1
                #i_int.next = 1
        else:
            reset.next = 0
 
    

    dut_depp = depp(clock,a_dstb,a_astb,a_write,a_wait,a_addr_reg,fr_rpi2B,to_rpi2B)
    dut_mul_ts = mul_ts(clock,fr_rpi2B,reset,tsenable,to_rpi2B)
    
 
      
    return myhdl.instances()    
示例#37
0
def Counter(out, clk, rst = 1):
    
    """ n-bit Counter
    
    out -- output signal with specified bit length
    clk -- clock
    rst -- active-low reset
    
    """
    
    n = len(out)
    tff_inst = [None for i in range(n)]
    not_inst = [None for i in range(n)]
    int_clk = [Signal(int(not out(i))) for i in range(n)]
    out_temp = [Signal(int(out(i))) for i in range(n)]
    
    tff_inst[0] = tff(out_temp[0], Signal(1), clk, rst)
    not_inst[0] = Not(int_clk[0], out_temp[0])
    for i in range(1, n):
        tff_inst[i] = tff(out_temp[i], Signal(1), int_clk[i - 1], rst)
        not_inst[i] = Not(int_clk[i], out_temp[i])
    
    @always_comb
    def connect_out_bits():
        for i in range(n):
            out.next[i] = out_temp[i]
    
    return instances()
示例#38
0
文件: vidmem.py 项目: sobuildit/rhea
def video_memory(glbl, vidmem_write, vidmem_read):
    """
    """
    assert vidmem_write.width == vidmem_read.width
    vmem = vidmem_write
    res = vmem.resolution
    mem = [Signal(intbv(0)[vmem.width:]) for _ in range(vmem.size)]

    clock, reset = glbl.clock, glbl.reset

    # address translation
    waddr = Signal(intbv(0, min=0, max=vmem.size))

    @always_comb
    def beh_addr():
        # @todo: this will be expensive, shortcut/hack ???
        waddr.next = vmem.hpxl + (vmem.vpxl * vmem.resolution[0])

    # write
    @always(clock.posedge)
    def beh_write():
        if vidmem_write.wr:
            mem[waddr].next = concat(vmem.red, vmem.green, vmem.blue)

    return myhdl.instances()
示例#39
0
def run_IM_cosim():
    # Initiate signals
    MAX_TIME = 1000000
    clock = Signal(0)
    MR = Signal(0, delay=10)
    MW = Signal(0, delay=10)
    address = Signal(intbv(0, 0, 2**32), delay=10)
    WD = Signal(intbv(0, 0, 2**32), delay=10)
    pyData = Signal(intbv(0, 0, 2**32))
    vData = Signal(intbv(0, 0, 2**32))

    # Build driver instances
    clock_driver = clock_generator(clock, period=20)
    addr_driver = random_signal(clock, address, seed=1)
    WD_driver = random_signal(clock, WD, seed=2)
    MR_driver = pulse_generator(clock, MR, delay=2)
    MW_driver = pulse_generator(clock, MW, delay=3)
    py_cosim = traceSignals(py_dm(clock, address, MW, MR, pyData, WD))
    v_cosim = v_dm(clock, MR, MW, address, WD, vData)
    read_test = match_test_report(clock,
                                  vData,
                                  pyData,
                                  a_name="v:",
                                  b_name="py:")

    sim = Simulation(instances())
    sim.run(MAX_TIME)
示例#40
0
文件: vidmem.py 项目: rowhit/rhea
def video_memory(glbl, vidmem_write, vidmem_read):
    """
    """
    assert vidmem_write.width == vidmem_read.width
    vmem = vidmem_write
    res = vmem.resolution
    mem = [Signal(intbv(0)[vmem.width:]) for _ in range(vmem.size)]

    clock, reset = glbl.clock, glbl.reset

    # address translation
    waddr = Signal(intbv(0, min=0, max=vmem.size))

    @always_comb
    def beh_addr():
        # @todo: this will be expensive, shortcut/hack ???
        waddr.next = vmem.hpxl + (vmem.vpxl * vmem.resolution[0])

    # write
    @always(clock.posedge)
    def beh_write():
        if vidmem_write.wr:
            mem[waddr].next = concat(vmem.red, vmem.green, vmem.blue)

    return myhdl.instances()
示例#41
0
def fifo_short(clock, reset, clear,
               datain, src_rdy_i, dst_rdy_o,
               dataout, src_rdy_o, dst_rdy_i):

    glbl = Global(clock, reset)
    wr = Signal(bool(0))
    rd = Signal(bool(0))

    args = Namespace(width=36, size=16, name='fifo_2clock_cascade')
    fbus = FIFOBus(width=args.width)
    # need to update the fbus refernces to reference the Signals in
    # the module port list (function arguments).
    fbus.write = wr
    fbus.write_data = datain
    fbus.read = rd
    fbus.read_data = dataout

    @always_comb
    def beh_assign1():
        wr.next = src_rdy_i & dst_rdy_o
        rd.next = dst_rdy_i & src_rdy_o

    @always_comb
    def beh_assign2():
        dst_rdy_o.next = not fbus.full
        src_rdy_o.next = not fbus.empty

    fifo_inst = fifo_fast(glbl, fbus, size=args.size)

    return myhdl.instances()
示例#42
0
def laserdriver(clock, reset, laserpin):
    duty_cnt = Signal(intbv(0, min=0, max=DUTY_CNTMAX))
    laser_cnt = Signal(intbv(0, min=0, max=PWMLENGTH))

    @always_comb
    def duty():
        if reset == 1:
            laserpin.next = 0
        elif laser_cnt < laser_cnt.max - 1:
            laserpin.next = 1
        else:
            laserpin.next = 0

    @always_seq(clock.posedge, reset)
    def dutygen():
        if duty_cnt >= duty_cnt.max - 1:
            duty_cnt.next = 0
            if laser_cnt >= laser_cnt.max - 1:
                laser_cnt.next = 0
            else:
                laser_cnt.next = laser_cnt + 1
        else:
            duty_cnt.next = duty_cnt + 1

    return instances()
示例#43
0
def procuder_consumer(clock_write, clock_read, fbus, start):
    # FIFO writer and reader
    _wr = Signal(bool(0))
    w = len(fbus.write_data)

    @instance
    def tb_always_wr():
        was_full = False
        wrd = modbv(0)[w:]
        while True:
            if start:
                break
            yield clock_write.posedge

        while True:
            yield clock_write.posedge
            if not fbus.full and was_full:
                was_full = False
                for _ in range(17):
                    yield clock_write.posedge
            elif not fbus.full:
                fbus.write_data.next = wrd
                _wr.next = True
                yield delay(1)
                if not fbus.full:
                    wrd[:] += 1
            else:
                _wr.next = False
                was_full = True

    @always_comb
    def tb_always_wr_gate():
        fbus.write.next = _wr and not fbus.full

    @instance
    def tb_always_rd():
        rdd = modbv(0)[w:]
        while True:
            if start:
                break
            yield clock_write.posedge

        while True:
            try:
                yield clock_read.posedge
                if not fbus.empty:
                    fbus.read.next = True
                else:
                    fbus.read.next = False

                if fbus.read_valid:
                    tmp = fbus.read_data
                    assert tmp == rdd, " %d != %d " % (tmp, rdd)
                    rdd[:] += 1
            except AssertionError as err:
                for _ in range(10):
                    yield clock_read.posedge
                raise err

    return myhdl.instances()
示例#44
0
    def top(self, reset, clk, pipeST_A_stage_i, pipeST_B_stage_i,
            pipeST_stage_o):

        # Operation happenning at the required stage inputs
        reg_stage_inst = []

        reg_stage_inst.append(
            self.block_atomic_oper(reset, clk, pipeST_A_stage_i[self.OPSTAGE],
                                   pipeST_B_stage_i[self.OPSTAGE],
                                   pipeST_stage_o[0]))

        for j in range(1, self.NB_PIPELINE_STAGES):

            reg_stage_inst.append(
                simple_reg_assign(reset, clk, pipeST_stage_o[j].data,
                                  self.reset_val, pipeST_stage_o[j - 1].data))
            reg_stage_inst.append(
                simple_reg_assign(reset, clk, pipeST_stage_o[j].sop, 0,
                                  pipeST_stage_o[j - 1].sop))
            reg_stage_inst.append(
                simple_reg_assign(reset, clk, pipeST_stage_o[j].eop, 0,
                                  pipeST_stage_o[j - 1].eop))
            reg_stage_inst.append(
                simple_reg_assign(reset, clk, pipeST_stage_o[j].valid, 0,
                                  pipeST_stage_o[j - 1].valid))
            reg_stage_inst.append(
                simple_reg_assign(reset, clk, pipeST_stage_o[j].channel, 0,
                                  pipeST_stage_o[j - 1].channel))

        return myhdl.instances()
示例#45
0
    def gen(self):
        idx = Signal(intbv(0, 0, self.parts))

        insts = []

        rd_parts = []
        for i in range(self.parts):
            s = Signal(intbv(0)[self.data_width:])
            insts.append(self.extract(s, i))
            rd_parts.append(s)

        @always_comb
        def comb():
            self.parent.RD.next = 0
            self.RD_DATA.next = rd_parts[idx]
            self.RD_EMPTY.next = self.parent.RD_EMPTY

            if self.RD and idx == self.parts - 1:
                self.parent.RD.next = 1

        @always_seq(self.RD_CLK.posedge, self.RD_RST)
        def seq():
            if self.RD:
                idx.next = 0
                if idx != self.parts - 1:
                    idx.next = idx + 1

        return instances()
示例#46
0
def TestKB():
    dat = Signal(bool(0))
    clk = Signal(bool(0))
    rst = ResetSignal(bool(0), active=1, isasync=True)
    code = Signal(intbv(0)[9:])
    finish = Signal(bool(0))
    
    inst = PS2Keyboard(code, finish, dat, clk, rst)

    the_data = [
        [0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 1],
        [0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 1]]

    @instance
    def stimulus():
        print('dat\tcode\t\tfinish')
        clk.next = 1
        yield delay(10)
        for k in range(2*11):
            bit = the_data[k//11][k%11]
            dat.next = bit 
            yield delay(10)
            clk.next = 0
            yield delay(10)
            clk.next = 1
            print(bit, f'{int(code):09b}', int(finish), sep='\t')

    return instances()
示例#47
0
文件: rst.py 项目: shangdawei/sds7102
def rst_sync(clk, rst_in, rst_out, n = 2):
    taps = [ Signal(False) for _ in range(n) ]

    @always(clk.posedge, rst_in.posedge)
    def rst_seq():
        if rst_in:
            for i in range(0, len(taps)):
                taps[i].next = 0
        else:
            for i in range(1, len(taps)):
                taps[i].next = taps[i-1]
            taps[0].next = 1

    if isinstance(rst_out, ResetSignal):
        active = rst_out.active
    else:
        active = 1

    @always_comb
    def rst_comb():
        if taps[len(taps)-1]:
            rst_out.next = not active
        else:
            rst_out.next = active

    return instances()
示例#48
0
def testBench():

    i_in, pc_in, i_out, pc_out = [Signal(intbv(0)[32:]) for i in range(4)]

    clk, rst, stall = [Signal(intbv(0)[1:]) for i in range(3)]

    latch_inst = toVHDL(latch_if_id, clk, rst, i_in, pc_in, i_out, pc_out,
                        stall)

    @instance
    def stimulus():
        for i in range(10):
            i_in.next, pc_in.next = [
                Signal(intbv(random.randint(0, 255))[32:]) for i in range(2)
            ]

            if random.random() > 0.10:
                clk.next = 1
            if random.random() > 0.75:
                rst.next = 1
            if random.random() > 0.5:
                stall.next = 1

            yield delay(1)
            print "Inputs: %i %i | clk: %i  rst: %i stall:%i | Output: %i %i" % (
                i_in, pc_in, clk, rst, stall, i_out, pc_out)
            clk.next = 0
            rst.next = 0
            stall.next = 0
            yield delay(1)

    return instances()
示例#49
0
文件: rst.py 项目: shangdawei/sds7102
def rstgen(rst, t, clk = None):
    """Reset generator

    The reset is asserted immediately.  If clk is not None the reset
    will be deasserted on the positive edge of clk.  Value is the
    asserted value for the reset signal and defaults to True.
    """

    internal_rst = Signal(False)

    @instance
    def rst_inst():
        internal_rst.next = 1
        yield delay(t)
        internal_rst.next = 0

    if clk is None:
        if isinstance(rst, ResetSignal):
            active = rst.active
        else:
            active = 1

        @always_comb
        def rst_comb():
            if internal_rst:
                rst.next = active
            else:
                rst.next = not active

    else:
        sync_inst = rst_sync(clk, internal_rst, rst)

    return instances()
示例#50
0
文件: led_mm_per.py 项目: wingel/rhea
def led_peripheral(glbl, regbus, leds, base_address=0x8240):
    """ LED memory-map peripheral
    This (rather silly) core will select different LED
    displays based on the memory-mapped select register.
    """

    ndrv = 3  # the number of different drivers
    regfile.base_address = base_address 
    
    clock, reset = glbl.clock, glbl.reset
    rleds = Signal(intbv(0)[len(leds):])

    # assign the LED port to the local register
    assign(leds, rleds)

    # memory-mapped registers
    greg = regbus.add(regfile, 'led')

    # led bus from each driver
    dled = Signals(intbv(0)[len(leds):0], ndrv)

    # instantiate different LED drivers
    led_insts = [None for _ in range(ndrv)]
    led_insts[0] = led_stroby(clock, reset, dled[0])
    led_insts[1] = led_count(clock, reset, dled[1])
    led_insts[2] = led_dance(clock, reset, dled[2])

    @always_seq(clock.posedge, reset=reset)
    def beh():
        for ii in range(ndrv):
            idx = regfile.select
            rleds.next = dled[idx-1]

    return myhdl.instances()
示例#51
0
def DualDelayer(
        timeout_short,
        timeout_long,
        clk,
        rst,
        interval_short, # Parameter (Seconds)
        interval_long,  # Parameter (Seconds)
        clk_freq, # Parameter (Hz)
    ):
    COUNTER_LONG_MAX  = int(interval_long  * clk_freq)
    COUNTER_SHORT_MAX = int(interval_short * clk_freq) 

    counter = Signal(intbv(0, min=0, max=COUNTER_LONG_MAX+1))

    @always(clk.posedge, rst.posedge)
    def do():
        if rst:
            counter.next = 0
            timeout_short.next = 0
            timeout_long.next = 0
        else:
            if counter >= COUNTER_SHORT_MAX:
                timeout_short.next = 1
            else:
                timeout_short.next = 0
            if counter >= COUNTER_LONG_MAX:
                timeout_long.next = 1
            else:
                timeout_long.next = 0
                counter.next = counter + 1

    return instances()