def test_create_constraints_to_file(tmpdir): # Construct the sample machine and graph machine = VirtualMachine(version=3, with_wrap_arounds=None) # TODO: define some extra monitor cores (how?) graph = MachineGraph("foo") tag1 = IPtagResource("1.2.3.4", 5, False, tag="footag") tag2 = ReverseIPtagResource(tag="bartag") v0 = SimpleMachineVertex(ResourceContainer(iptags=[tag1], reverse_iptags=[tag2]), constraints=[ChipAndCoreConstraint(1, 1, 3)]) graph.add_vertex(v0) v0_id = ident(v0) v1 = MachineSpiNNakerLinkVertex(2, constraints=[ChipAndCoreConstraint(1, 1)]) v1.set_virtual_chip_coordinates(0, 2) graph.add_vertex(v1) v1_id = ident(v1) algo = CreateConstraintsToFile() fn = tmpdir.join("foo.json") filename, mapping = algo(graph, machine, str(fn)) assert filename == str(fn) for vid in mapping: assert vid in [v0_id, v1_id] assert vid == ident(mapping[vid]) obj = json.loads(fn.read()) baseline = [{ "type": "reserve_resource", "location": None, "reservation": [0, 1], "resource": "cores" }, { "type": "location", "location": [1, 1], "vertex": v0_id }, { "type": "resource", "resource": "cores", "range": [3, 4], "vertex": v0_id }, { "type": "resource", "resource": "iptag", "range": [0, 1], "vertex": v0_id }, { "type": "resource", "resource": "reverse_iptag", "range": [0, 1], "vertex": v0_id }, { "type": "route_endpoint", "direction": "south", "vertex": v1_id }, { "type": "location", "location": [1, 0], "vertex": v1_id }] assert obj == baseline
def do_run(self): sim.setup(timestep=1.0, n_boards_required=1) sim.set_number_of_neurons_per_core(sim.IF_curr_exp, 100) machine = globals_variables.get_simulator().machine input1 = sim.Population(1, sim.SpikeSourceArray(spike_times=[0]), label="input1") input2 = sim.Population(1, sim.SpikeSourceArray(spike_times=[0]), label="input2") pop_1 = sim.Population(5, sim.IF_curr_exp(), label="pop_1") pop_2 = sim.Population(5, sim.IF_curr_exp(), label="pop_2") sim.Projection(input1, pop_1, sim.AllToAllConnector(), synapse_type=sim.StaticSynapse(weight=5, delay=1)) sim.Projection(input2, pop_2, sim.AllToAllConnector(), synapse_type=sim.StaticSynapse(weight=5, delay=1)) # Make sure there is stuff at the cores specified in the cfg file input1.set_constraint(ChipAndCoreConstraint(0, 0, 1)) input2.set_constraint(ChipAndCoreConstraint(0, 0, 3)) # While there must be a chip 0,0 chip 1,1 could be missing if machine.is_chip_at(1, 1): pop_1.set_constraint(ChipAndCoreConstraint(1, 1, 1)) # Make sure there is stuff at a core not specified in the cfg file pop_2.set_constraint(ChipAndCoreConstraint(0, 0, 2)) sim.run(500) provenance_files = self.get_app_iobuf_files() sim.end() self.assertIn("iobuf_for_chip_0_0_processor_id_1.txt", provenance_files) self.assertNotIn("iobuf_for_chip_0_0_processor_id_2.txt", provenance_files) self.assertIn("iobuf_for_chip_0_0_processor_id_3.txt", provenance_files) self.assertNotIn("iobuf_for_chip_0_0_processor_id_4.txt", provenance_files) if machine.is_chip_at(1, 1): self.assertIn("iobuf_for_chip_1_1_processor_id_1.txt", provenance_files) self.assertNotIn("iobuf_for_chip_1_1_processor_id_2.txt", provenance_files)
def _add_power_monitor_for_chip(chip, machine_graph, application_graph, graph_mapper, sampling_frequency, n_samples_per_recording): # build constraint constraint = ChipAndCoreConstraint(chip.x, chip.y) # build machine vert machine_vertex = ChipPowerMonitorMachineVertex( label=_LABEL.format("machine", chip.x, chip.y), sampling_frequency=sampling_frequency, n_samples_per_recording=n_samples_per_recording, constraints=[constraint]) # add vert to graph machine_graph.add_vertex(machine_vertex) # deal with app graphs if needed if application_graph is not None: # build app vertex vertex_slice = Slice(0, 0) application_vertex = ChipPowerMonitor( label=_LABEL.format("application", chip.x, chip.y), constraints=[constraint], sampling_frequency=sampling_frequency, n_samples_per_recording=n_samples_per_recording) # add to graph application_graph.add_vertex(application_vertex) # update graph mapper graph_mapper.add_vertex_mapping(machine_vertex, vertex_slice, application_vertex)
def test_1_chip_no_pre_allocated_too_much_sdram(self): machine = virtual_machine(width=8, height=8) graph = ApplicationGraph("Test") partitioner = SplitterPartitioner() eight_meg = 8 * 1024 * 1024 # add graph vertices which reside on 0,0 for _ in range(0, 13): vertex = SimpleTestVertex( constraints=[ChipAndCoreConstraint(x=0, y=0)], n_atoms=1, fixed_sdram_value=eight_meg) vertex.splitter = SplitterSliceLegacy() graph.add_vertex(vertex) # add pre-allocated resources for cores on 0,0 pre_allocated_res = PreAllocatedResourceContainer() # run partitioner that should go boom try: partitioner(graph, machine, plan_n_time_steps=None, pre_allocated_resources=pre_allocated_res) except Exception: raise Exception("should have blown up here")
def __init__(self, iid=0, x_coord=None, y_coord=None): label = f"pe/{iid}" constraints = None if x_coord is not None: if y_coord is not None: label = f"pe/{x_coord}-{y_coord}/{iid}" constraints = [ ChipAndCoreConstraint(x=int(x_coord), y=int(y_coord)) ] else: print("incompatible coordinates given") elif y_coord is not None: print("incompatible coordinates given") super(Pkt_Extractor_Vertex, self).__init__(label=label, binary_name="pkt_extractor.aplx", constraints=constraints) # configuration structure self.CONFIGURATION_BYTES = len(self.config) # configuration data plus application core SDRAM usage self.sdram_fixed = (SYSTEM_BYTES_REQUIREMENT + self.CONFIGURATION_BYTES)
def test_1_chip_over_pre_allocated(self): machine = virtual_machine(width=8, height=8) graph = ApplicationGraph("Test") partitioner = SplitterPartitioner() # add graph vertices which reside on 0,0 for _ in range(0, 13): vertex = SimpleTestVertex( constraints=[ChipAndCoreConstraint(x=0, y=0)], n_atoms=1) vertex.splitter = SplitterSliceLegacy() graph.add_vertex(vertex) # add pre-allocated resources for cores on 0,0 core_pre = CoreResource(chip=machine.get_chip_at(0, 0), n_cores=5) pre_allocated_res = PreAllocatedResourceContainer( core_resources=[core_pre]) # run partitioner that should go boom try: partitioner(graph, machine, plan_n_time_steps=None, pre_allocated_resources=pre_allocated_res) raise Exception("should have blown up here") except PacmanInvalidParameterException: pass
def test_1_chip_pre_allocated_same_core(self): machine = VirtualMachine(width=8, height=8) graph = ApplicationGraph("Test") partitioner = PartitionAndPlacePartitioner() # add graph vertices which reside on 0,0 for p in range(0, 13): graph.add_vertex( SimpleTestVertex( constraints=[ChipAndCoreConstraint(x=0, y=0, p=p)], n_atoms=1)) # add pre-allocated resources for cores on 0,0 core_pre = SpecificCoreResource(chip=machine.get_chip_at(0, 0), cores=[4]) pre_allocated_res = PreAllocatedResourceContainer( specific_core_resources=[core_pre]) # run partitioner that should go boom try: partitioner(graph, machine, pre_allocated_res) raise Exception("should have blown up here") except PacmanValueError: pass except Exception: raise Exception("should have blown up here")
def test_1_chip_pre_allocated_too_much_sdram(self): machine = virtual_machine(width=8, height=8) graph = ApplicationGraph("Test") partitioner = SplitterPartitioner() eight_meg = 8 * 1024 * 1024 # add graph vertices which reside on 0,0 for _ in range(0, 13): vertex = SimpleTestVertex( constraints=[ChipAndCoreConstraint(x=0, y=0)], n_atoms=1, fixed_sdram_value=eight_meg) vertex.splitter = SplitterSliceLegacy() graph.add_vertex(vertex) # add pre-allocated resources for cores on 0,0 twenty_meg = ConstantSDRAM(20 * 1024 * 1024) core_pre = SpecificChipSDRAMResource( chip=machine.get_chip_at(0, 0), sdram_usage=twenty_meg) pre_allocated_res = PreAllocatedResourceContainer( specific_sdram_usage=[core_pre]) # run partitioner that should go boom try: partitioner(graph, machine, plan_n_time_steps=None, pre_allocated_resources=pre_allocated_res) raise Exception("should have blown up here") except PacmanPartitionException: pass except Exception: exc_info = sys.exc_info() six.reraise(*exc_info)
def run(self, mbs, x, y): # setup system sim.setup(model_binary_module=( speed_tracker_with_protocol_search_c_code_version)) # build verts reader = SDRAMReaderAndTransmitterWithProtocol(mbs) reader.add_constraint(ChipAndCoreConstraint(x=x, y=y)) receiver = PacketGathererWithProtocol() # add verts to graph sim.add_machine_vertex_instance(reader) sim.add_machine_vertex_instance(receiver) # build and add edge to graph sim.add_machine_edge_instance(MachineEdge(reader, receiver), "TRANSMIT") machine = sim.machine() if machine.is_chip_at(x, y): return self._do_run(reader, receiver, mbs) else: sim.stop() return None, False, False, "", 0
def test_1_chip_pre_allocated_too_much_sdram(self): machine = VirtualMachine(width=8, height=8) graph = ApplicationGraph("Test") partitioner = PartitionAndPlacePartitioner() eight_meg = 8 * 1024 * 1024 # add graph vertices which reside on 0,0 for _ in range(0, 13): graph.add_vertex( SimpleTestVertex(constraints=[ChipAndCoreConstraint(x=0, y=0)], n_atoms=1, fixed_sdram_value=eight_meg)) # add pre-allocated resources for cores on 0,0 twenty_meg = 20 * 1024 * 1024 core_pre = SpecificChipSDRAMResource(chip=machine.get_chip_at(0, 0), sdram_usage=twenty_meg) pre_allocated_res = PreAllocatedResourceContainer( specific_sdram_usage=[core_pre]) # run partitioner that should go boom try: partitioner(graph, machine, pre_allocated_res) raise Exception("should have blown up here") except PacmanPartitionException: pass except Exception: raise Exception("should have blown up here")
def constraint_from_json(json_dict, graph=None): if json_dict["class"] == "BoardConstraint": return BoardConstraint(json_dict["board_address"]) if json_dict["class"] == "ChipAndCoreConstraint": if "p" in json_dict: p = json_dict["p"] else: p = None return ChipAndCoreConstraint(json_dict["x"], json_dict["y"], p) if json_dict["class"] == "ContiguousKeyRangeContraint": return ContiguousKeyRangeContraint() if json_dict["class"] == "FixedKeyAndMaskConstraint": if "key_list_function" in json_dict: raise NotImplementedError("key_list_function {}".format( json_dict["key_list_function"])) return FixedKeyAndMaskConstraint( key_masks_from_json(json_dict["keys_and_masks"])) if json_dict["class"] == "FixedMaskConstraint": return FixedMaskConstraint(json_dict["mask"]) if json_dict["class"] == "FixedVertexAtomsConstraint": return FixedVertexAtomsConstraint(json_dict["size"]) if json_dict["class"] == "MaxVertexAtomsConstraint": return MaxVertexAtomsConstraint(json_dict["size"]) if json_dict["class"] == "RadialPlacementFromChipConstraint": return RadialPlacementFromChipConstraint(json_dict["x"], json_dict["y"]) if json_dict["class"] == "SameChipAsConstraint": return SameChipAsConstraint(vertex_lookup(json_dict["vertex"], graph)) if json_dict["class"] == "SameAtomsAsVertexConstraint": return SameAtomsAsVertexConstraint( vertex_lookup(json_dict["vertex"], graph)) raise NotImplementedError("constraint {}".format(json_dict["class"]))
def test_virtual_vertices_spreader(): """ Test that the placer works with a virtual vertex """ # Create a graph with a virtual vertex machine_graph = MachineGraph("Test") virtual_vertex = MachineSpiNNakerLinkVertex( spinnaker_link_id=0, label="Virtual") machine_graph.add_vertex(virtual_vertex) # These vertices are fixed on 0, 0 misc_vertices = list() for i in range(3): misc_vertex = SimpleMachineVertex( resources=ResourceContainer(), constraints=[ ChipAndCoreConstraint(0, 0)], label="Fixed_0_0_{}".format(i)) machine_graph.add_vertex(misc_vertex) misc_vertices.append(misc_vertex) # These vertices are 1-1 connected to the virtual vertex one_to_one_vertices = list() for i in range(16): one_to_one_vertex = SimpleMachineVertex( resources=ResourceContainer(), label="Vertex_{}".format(i)) machine_graph.add_vertex(one_to_one_vertex) edge = MachineEdge(virtual_vertex, one_to_one_vertex) machine_graph.add_edge(edge, "SPIKES") one_to_one_vertices.append(one_to_one_vertex) n_keys_map = DictBasedMachinePartitionNKeysMap() partition = machine_graph.get_outgoing_edge_partition_starting_at_vertex( virtual_vertex, "SPIKES") n_keys_map.set_n_keys_for_partition(partition, 1) # Get and extend the machine for the virtual chip machine = virtual_machine(width=8, height=8) extended_machine = MallocBasedChipIdAllocator()(machine, machine_graph) # Do placements placements = SpreaderPlacer()( machine_graph, extended_machine, n_keys_map, plan_n_timesteps=1000) # The virtual vertex should be on a virtual chip placement = placements.get_placement_of_vertex(virtual_vertex) assert machine.get_chip_at(placement.x, placement.y).virtual # The 0, 0 vertices should be on 0, 0 for vertex in misc_vertices: placement = placements.get_placement_of_vertex(vertex) assert placement.x == placement.y == 0 # The other vertices should *not* be on a virtual chip for vertex in one_to_one_vertices: placement = placements.get_placement_of_vertex(vertex) assert not machine.get_chip_at(placement.x, placement.y).virtual
def test_chip_and_core_constraint(self): c1 = ChipAndCoreConstraint(1, 2) self.assertEqual(c1.x, 1) self.assertEqual(c1.y, 2) self.assertEqual(c1.p, None) self.assertEqual(c1.location, {"x": 1, "y": 2, "p": None}) self.assertEqual(c1, ChipAndCoreConstraint(1, 2)) self.assertEqual(str(c1), 'ChipAndCoreConstraint(x=1, y=2, p=None)') c2 = ChipAndCoreConstraint(2, 1) c3 = ChipAndCoreConstraint(1, 2, 3) self.assertNotEqual(c1, c2) self.assertNotEqual(c1, c3) self.assertNotEqual(c1, "1.2.3.4") d = {} d[c1] = 1 d[c2] = 2 d[c3] = 3 self.assertEqual(len(d), 3)
def __call__(self, machine, machine_graph, n_samples_per_recording, sampling_frequency, application_graph=None): """ Adds chip power monitor vertices on Ethernet connected chips as\ required. :param ~.Machine machine: :param ~.MachineGraph machine_graph: :param int n_samples_per_recording: :param int sampling_frequency: :param ~.ApplicationGraph application_graph: """ # pylint: disable=too-many-arguments # create progress bar progress = ProgressBar(machine.n_chips, "Adding Chip power monitors to Graph") app_vertex = None if application_graph is not None: app_vertex = ChipPowerMonitor( label="ChipPowerMonitor", sampling_frequency=sampling_frequency, n_samples_per_recording=n_samples_per_recording) application_graph.add_vertex(app_vertex) for chip in progress.over(machine.chips): machine_vertex = app_vertex.create_machine_vertex( vertex_slice=None, resources_required=None, label=_LABEL.format("machine", chip.x, chip.y), constraints=[ChipAndCoreConstraint(chip.x, chip.y)]) machine_graph.add_vertex(machine_vertex) else: for chip in progress.over(machine.chips): machine_vertex = ChipPowerMonitorMachineVertex( label=_LABEL.format("machine", chip.x, chip.y), constraints=[ChipAndCoreConstraint(chip.x, chip.y)], app_vertex=app_vertex, sampling_frequency=sampling_frequency, n_samples_per_recording=n_samples_per_recording) machine_graph.add_vertex(machine_vertex)
def set_virtual_chip_coordinates(self, virtual_chip_x, virtual_chip_y): if virtual_chip_x is not None and virtual_chip_y is not None: self._virtual_chip_x = virtual_chip_x self._virtual_chip_y = virtual_chip_y self.add_constraint(ChipAndCoreConstraint( self._virtual_chip_x, self._virtual_chip_y)) if (self._app_vertex is not None and self._app_vertex.virtual_chip_x is None and self._app_vertex.virtual_chip_y is None): self._app_vertex.set_virtual_chip_coordinates()
def __new_mach_gatherer( ethernet_chip, default_report_directory, write_data_speed_up_report): return DataSpeedUpPacketGatherMachineVertex( x=ethernet_chip.x, y=ethernet_chip.y, ip_address=ethernet_chip.ip_address, constraints=[ChipAndCoreConstraint( x=ethernet_chip.x, y=ethernet_chip.y)], report_default_directory=default_report_directory, write_data_speed_up_report=write_data_speed_up_report)
def add_placement_constraint(self, x, y, p=None): """ Add a placement constraint :param int x: The x-coordinate of the placement constraint :param int y: The y-coordinate of the placement constraint :param int p: The processor ID of the placement constraint (optional) """ globals_variables.get_simulator().verify_not_running() self.__vertex.add_constraint(ChipAndCoreConstraint(x, y, p)) # state that something has changed in the population, self.__change_requires_mapping = True
def _add_mach_lpg_vertex(self, chip, params): """ Adds a LPG vertex to a machine graph without an associated\ application graph. :param ~.Chip chip: :param LivePacketGatherParameters params: :rtype: LivePacketGatherMachineVertex """ vtx = LivePacketGatherMachineVertex( params, constraints=[ChipAndCoreConstraint(x=chip.x, y=chip.y)]) self._machine_graph.add_vertex(vtx) return vtx
def test_deal_with_constraint_placement_vertices_have_vertices(self): self.bp = RadialPlacer(self.machine, self.graph) self.vertex1.add_constraint(ChipAndCoreConstraint(1, 5, 2)) self.assertIsInstance(self.vertex1.constraints[0], ChipAndCoreConstraint) self.vertex2.add_constraint(ChipAndCoreConstraint(3, 5, 7)) self.vertex3.add_constraint(ChipAndCoreConstraint(2, 4, 6)) self.vertex4.add_constraint(ChipAndCoreConstraint(6, 7, 16)) self.vertices = list() self.vertices.append(self.vertex1) self.vertices.append(self.vertex2) self.vertices.append(self.vertex3) self.vertices.append(self.vertex4) self.edges = list() self.graph = MachineGraph(self.vertices, self.edges) self.graph_mapper = GraphMapper() self.graph_mapper.add_vertices(self.vertices, self.vert1) placements = self.bp.place(self.graph, self.graph_mapper) for placement in placements.placements: print(placement.vertex.label, placement.vertex.n_atoms, 'x:', placement.x, 'y:', placement.y, 'p:', placement.p)
def __init__(self, iid=0, x_coord=None, y_coord=None, nkeys=1, throttle=0, use_payload=True): label = f"pi/{iid}" constraints = None if x_coord is not None: if y_coord is not None: label = f"pi/{x_coord}-{y_coord}/{iid}" constraints = [ ChipAndCoreConstraint(x=int(x_coord), y=int(y_coord)) ] else: print("incompatible coordinates given") elif y_coord is not None: print("incompatible coordinates given") super(Pkt_Injector_Vertex, self).__init__(label=label, binary_name="pkt_injector.aplx", constraints=constraints) # number of routing keys to be used self.NKEYS = nkeys # injection links if self.NKEYS == 1: self.inj_lnk = f"inj_link{x_coord}-{y_coord}/{iid}" else: self.inj_lnk = [] for k in range(self.NKEYS): self.inj_lnk.append(f"inj_link{x_coord}-{y_coord}/{iid}/{k}") # throttle control: wait "cycles" between sending packets self.throttle = throttle # use packets with payloads and check for missing packets self.use_payload = use_payload # size of configuration structure in SDRAM self.CONFIGURATION_BYTES = len(self.config) # size of routing keys structure in SDRAM self.ROUTING_BYTES = (self.NKEYS + 1) * BYTES_PER_WORD # total SDRAM usage self.sdram_fixed = (SYSTEM_BYTES_REQUIREMENT + self.CONFIGURATION_BYTES + self.ROUTING_BYTES)
def test_deal_with_constraint_placement_vertices_dont_have_vertex(self): self.vertex2.add_constraint(ChipAndCoreConstraint(3, 5, 7)) self.vertex3.add_constraint(RadialPlacementFromChipConstraint(2, 4)) placements = RadialPlacer()(self.mach_graph, self.machine, 100) for placement in placements.placements: if placement.vertex == self.vertex2: self.assertEqual(placement.x, 3) self.assertEqual(placement.y, 5) self.assertEqual(placement.p, 7) if placement.vertex == self.vertex3: self.assertEqual(placement.x, 2) self.assertEqual(placement.y, 4) self.assertEqual(len(self.vertices), len(placements))
def __init__(self, label): args = LivePacketGatherParameters( port=globals.ack_port, hostname=globals.host, strip_sdp=True, message_type=EIEIOType.KEY_PAYLOAD_32_BIT, use_payload_prefix=False, payload_as_time_stamps=False) machine_vertex = LivePacketGatherMachineVertex( args, label=label, constraints=[ChipAndCoreConstraint(x=0, y=0)]) super(Extractor, self).__init__(label, 1, [machine_vertex])
def __new_app_gatherer(ethernet_chip, vertex_to_chip_map, default_report_directory, write_data_speed_up_reports): return DataSpeedUpPacketGather( x=ethernet_chip.x, y=ethernet_chip.y, ip_address=ethernet_chip.ip_address, constraints=[ ChipAndCoreConstraint(x=ethernet_chip.x, y=ethernet_chip.y) ], extra_monitors_by_chip=vertex_to_chip_map, report_default_directory=default_report_directory, write_data_speed_up_reports=write_data_speed_up_reports)
def set_virtual_chip_coordinates(self, virtual_chip_x, virtual_chip_y): if virtual_chip_x is not None and virtual_chip_y is not None: self._virtual_chip_x = virtual_chip_x self._virtual_chip_y = virtual_chip_y if len(self._machine_vertices) != 0: for machine_vertex in self._machine_vertices: if (machine_vertex.virtual_chip_x != self._virtual_chip_x or machine_vertex.virtual_chip_y != virtual_chip_y): machine_vertex.set_virtual_chip_coordinates( self._virtual_chip_x, self._virtual_chip_y) else: self.add_constraint(ChipAndCoreConstraint( self._virtual_chip_x, self._virtual_chip_y))
def _add_lpg_vertex(self, app_graph, mapper, m_graph, chip, params): # pylint: disable=too-many-arguments if app_graph is not None: _slice = Slice(0, 0) app_vtx = self._create_vertex(LivePacketGather, params) app_graph.add_vertex(app_vtx) resources = app_vtx.get_resources_used_by_atoms(_slice) m_vtx = app_vtx.create_machine_vertex(_slice, resources) mapper.add_vertex_mapping(m_vtx, _slice, app_vtx) else: m_vtx = self._create_vertex(LivePacketGatherMachineVertex, params) m_vtx.add_constraint(ChipAndCoreConstraint(x=chip.x, y=chip.y)) m_graph.add_vertex(m_vtx) return m_vtx
def _add_lpg_vertex(self, app_graph, mapper, m_graph, chip, lpg_params): if app_graph is not None: vtx_slice = Slice(0, 0) app_vtx = self._create_vertex(LivePacketGather, lpg_params) app_graph.add_vertex(app_vtx) resources_required = app_vtx.get_resources_used_by_atoms( vtx_slice) m_vtx = app_vtx.create_machine_vertex( vtx_slice, resources_required) mapper.add_vertex_mapping(m_vtx, vtx_slice, app_vtx) else: m_vtx = self._create_vertex( LivePacketGatherMachineVertex, lpg_params) m_vtx.add_constraint(ChipAndCoreConstraint(x=chip.x, y=chip.y)) m_graph.add_vertex(m_vtx) return m_vtx
def _add_app_lpg_vertex(self, chip, params): """ Adds a LPG vertex to a machine graph that has an associated\ application graph. :param ~.Chip chip: :param LivePacketGatherParameters params: :rtype: LivePacketGatherMachineVertex """ app_vtx = LivePacketGather(params) self._application_graph.add_vertex(app_vtx) # No need to handle resources when allocating; LPG has core to itself vtx = app_vtx.create_machine_vertex( vertex_slice=None, resources_required=None, label="LivePacketGatherer", constraints=[ChipAndCoreConstraint(x=chip.x, y=chip.y)]) self._machine_graph.add_vertex(vtx) return vtx
def test_chip_and_core_constraint(self): c1 = ChipAndCoreConstraint(1, 2) self.constraint_there_and_back(c1) c2 = ChipAndCoreConstraint(1, 2, 3) self.constraint_there_and_back(c2)
def run(self, mbs, number_of_repeats): # setup system sim.setup(model_binary_module=( test_extra_monitor_core_data_extraction_multiple_locations), n_chips_required=49 * 2) # build vertices locs = [(0, 0), (2, 2), (7, 7), (3, 0), (1, 0), (0, 1), (3, 3), (4, 4), (5, 5), (3, 5), (4, 0), (7, 4), (8, 4), (4, 8), (11, 11), (11, 0), (0, 11), (6, 3), (0, 6)] writers = list() for chip_x, chip_y in locs: writer = SDRAMWriter(mbs, constraint=ChipAndCoreConstraint( chip_x, chip_y)) # add vertices to graph sim.add_machine_vertex_instance(writer) writers.append(writer) sim.run(12) # get placements for extraction placements = sim.placements() machine = sim.machine() extra_monitor_vertices = sim.globals_variables. \ get_simulator()._last_run_outputs[ 'MemoryExtraMonitorVertices'] extra_monitor_gatherers = sim.globals_variables. \ get_simulator()._last_run_outputs[ 'MemoryMCGatherVertexToEthernetConnectedChipMapping'] time_out_setter = extra_monitor_gatherers[(0, 0)] time_out_setter.set_cores_for_data_extraction(sim.transceiver(), extra_monitor_vertices, placements) for _ in range(0, number_of_repeats): for writer in writers: writer_placement = placements.get_placement_of_vertex(writer) writer_chip = \ machine.get_chip_at(writer_placement.x, writer_placement.y) writer_nearest_ethernet = machine.get_chip_at( writer_chip.nearest_ethernet_x, writer_chip.nearest_ethernet_y) receiver = None gatherer = extra_monitor_gatherers[(writer_nearest_ethernet.x, writer_nearest_ethernet.y)] for vertex in extra_monitor_vertices: placement = placements.get_placement_of_vertex(vertex) if (placement.x == writer_placement.x and placement.y == writer_placement.y): receiver = vertex start = float(time.time()) data = gatherer.get_data( sim.transceiver(), placements.get_placement_of_vertex(receiver), self._get_data_region_address(sim.transceiver(), writer_placement), writer.mbs_in_bytes) end = float(time.time()) print("time taken to extract {} MB is {}. MBS of {}".format( mbs, end - start, (mbs * 8) / (end - start))) self._check_data(data) time_out_setter.unset_cores_for_data_extraction( sim.transceiver(), extra_monitor_vertices, placements)
test_retransmission_phase_on_multi_cores.\ sdram_reader_and_transmitter_with_protocol import \ SDRAMReaderAndTransmitterWithProtocol import time from spinnaker_graph_front_end.examples import \ test_retransmission_phase_on_multi_cores # data to write mbs = 1.0 # setup system sim.setup(model_binary_module=test_retransmission_phase_on_multi_cores) # build verts reader = SDRAMReaderAndTransmitterWithProtocol(mbs) reader.add_constraint(ChipAndCoreConstraint(x=1, y=1)) receiver = PacketGathererWithProtocol() # add verts to graph sim.add_machine_vertex_instance(reader) sim.add_machine_vertex_instance(receiver) # build and add edge to graph sim.add_machine_edge_instance(MachineEdge(reader, receiver), "TRANSMIT") # run forever (to allow better speed testing) sim.run() # get placements for extraction placements = sim.placements()