def test_1(self): sys = py4hw.HWSystem() a = sys.wire("a", 32) b = sys.wire("b", 32) c = sys.wire("c", 32) r1 = sys.wire("r1", 32) r2 = sys.wire("r2", 32) r3 = sys.wire("r3", 32) py4hw.And2(sys, "and1", a, b, r1) py4hw.And2(sys, "and2", a, c, r2) py4hw.And2(sys, "and3", b, c, r3) py4hw.Constant(sys, "a", 0xF, a) py4hw.Constant(sys, "b", 0xA, b) py4hw.Constant(sys, "c", 0x5, c) py4hw.Scope(sys, "r1 (0xF & 0xA)", r1) py4hw.Scope(sys, "r2 (0xF & 0x5)", r2) py4hw.Scope(sys, "r3 (0xA & 0x5)", r3) sys.getSimulator().clk(1) assert (r1.get() == 10) assert (r2.get() == 5) assert (r3.get() == 0)
def test_1(self): sys = py4hw.HWSystem() a = sys.wire("a", 32) b = sys.wire("b", 32) r1 = sys.wire("r", 32) py4hw.Constant(sys, "a", 10, a) py4hw.Constant(sys, "b", 20, b) py4hw.Add(sys, "add1", a, b, r1) sys.getSimulator().clk(1) assert (r1.get() == 30)
def test_printHierarchyWithValuesFormat(self): sys = py4hw.HWSystem() a = sys.wire("a", 32) b = sys.wire("b", 32) c = sys.wire("c", 32) r = sys.wire("r", 32) py4hw.Constant(sys, "a", 0xF7F7, a) py4hw.Constant(sys, "b", 0x7685, b) py4hw.Constant(sys, "c", 0x3452, c) py4hw.And(sys, 'andx', [a, b, c], r) py4hw.debug.printHierarchyWithValues(sys, format="{}")
def test_And_integrity(self): sys = py4hw.HWSystem() a = sys.wire("a", 32) b = sys.wire("b", 32) c = sys.wire("c", 32) r = sys.wire("r", 32) py4hw.Constant(sys, "a", 0xF7F7, a) py4hw.Constant(sys, "b", 0x7685, b) py4hw.Constant(sys, "c", 0x3452, c) py4hw.And(sys, 'andx', [a, b, c], r) py4hw.debug.checkIntegrity(sys)
def test_noneEqual(self): sys = py4hw.HWSystem() ins = sys.wires('wi', 3, 8) py4hw.Constant(sys, 'i0', 3, ins[0]) py4hw.Constant(sys, 'i1', 7, ins[1]) py4hw.Constant(sys, 'i2', 9, ins[2]) r = sys.wire('r', 1) py4hw.AnyEqual(sys, 'any', ins, r) sys.getSimulator().clk(1) assert (r.get() == 0)
def test_And(self): sys = py4hw.HWSystem() a = sys.wire("a", 32) b = sys.wire("b", 32) c = sys.wire("c", 32) r = sys.wire("r", 32) py4hw.Constant(sys, "a", 0xF7F7, a) py4hw.Constant(sys, "b", 0x7685, b) py4hw.Constant(sys, "c", 0x3452, c) py4hw.And(sys, 'andx', [a, b, c], r) sys.getSimulator().clk(1) assert (r.get() == 0x3400)
def test_1(self): sys = py4hw.HWSystem() reset = sys.wire('reset', 1) inc = sys.wire('inc', 1) count = sys.wire('count', 8) carry = sys.wire('carry', 1) py4hw.Constant(sys, 'reset', 0, reset) py4hw.Constant(sys, 'inc', 1, inc) counter = py4hw.ModuloCounter(sys, 'counter', 3, reset, inc, count, carry) rtlgen = py4hw.VerilogGenerator(counter) print(rtlgen.getVerilog())
def test_Integrity(self): sys = py4hw.HWSystem() a = sys.wire("a", 32) b = sys.wire("b", 32) c = sys.wire("c", 32) r1 = sys.wire("r", 32) r2 = sys.wire("r2", 32) py4hw.Add(sys, "add1", a, b, r1) py4hw.Add(sys, "add2", r1, c, r2) py4hw.Constant(sys, "a", 10, a) py4hw.Constant(sys, "b", 20, b) py4hw.Constant(sys, "c", 5, c) py4hw.Scope(sys, "r2", r2) py4hw.debug.checkIntegrity(sys)
def test_sub1(self): sys = py4hw.HWSystem() a = sys.wire('a', 23) b = sys.wire('b', 23) r = sys.wire('r', 24) va = 1623049 vb = 6146853 vr = (va - vb) & ((1 << 24) - 1) py4hw.Constant(sys, 'a', va, a) py4hw.Constant(sys, 'b', vb, b) py4hw.Sub(sys, 'r', a, b, r) sys.getSimulator().clk(1) assert (r.get() == vr)
def test_EqualWire(self): print('check values = 5') sys = py4hw.HWSystem() a = sys.wire("a", 3) b = sys.wire("b", 3) c = sys.wire("c", 3) r1 = sys.wire("r1", 1) r2 = sys.wire("r2", 1) py4hw.Constant(sys, "a", 3, a) py4hw.Constant(sys, "b", 3, b) py4hw.Constant(sys, "c", 5, c) py4hw.Equal(sys, 'equal1', a, b, r1) py4hw.Equal(sys, 'equal2', a, c, r2) sys.getSimulator().clk(1) assert (r1.get() == 1) assert (r2.get() == 0)
def test_integrity(self): sys = py4hw.HWSystem() a = sys.wire("a", 2) r = sys.wire("r", 1) py4hw.Constant(sys, "a", 0, a) py4hw.EqualConstant(sys, 'equal', a, 0, r) py4hw.debug.checkIntegrity(sys)
def test_notEqual(self): sys = py4hw.HWSystem() a = sys.wire("a", 2) r = sys.wire("r", 1) py4hw.Constant(sys, "a", 3, a) py4hw.EqualConstant(sys, 'equal', a, 0, r) sys.getSimulator().clk(1) assert (r.get() == 0)
def test_printHierarchy(self): sys = py4hw.HWSystem() a = sys.wire("a", 32) b = sys.wire("b", 32) c = sys.wire("c", 32) r1 = sys.wire("r1", 32) r2 = sys.wire("r2", 32) r3 = sys.wire("r3", 32) py4hw.And2(sys, "and1", a, b, r1) py4hw.And2(sys, "and2", a, c, r2) py4hw.And2(sys, "and3", b, c, r3) py4hw.Constant(sys, "a", 0xF, a) py4hw.Constant(sys, "b", 0xA, b) py4hw.Constant(sys, "c", 0x5, c) py4hw.Scope(sys, "r1 (0xF & 0xA)", r1) py4hw.Scope(sys, "r2 (0xF & 0x5)", r2) py4hw.Scope(sys, "r3 (0xA & 0x5)", r3) py4hw.debug.printHierarchy(sys)
def test_integrity(self): sys = py4hw.HWSystem() a = sys.wire("a", 2) bits = sys.wires('b', 2, 1) minterm = sys.wire('minterm', 1) py4hw.BitsLSBF(sys, 'bits', a, bits) py4hw.Minterm(sys, 'minterm', bits, 0, minterm) py4hw.Constant(sys, "a", 0, a) for i in range(len(bits)): py4hw.Scope(sys, 'b{}'.format(i), bits[i]) py4hw.Scope(sys, 'minterm_5', minterm) py4hw.debug.checkIntegrity(sys)
def __init__(self, parent, name, a, c, r): super().__init__(parent, name) self.addIn('a', a) self.addIn('c', c) self.addOut('r', r) aux1 = self.wire('aux1', a.getWidth()) aux2 = self.wire('aux2', a.getWidth()) aux3 = self.wire('aux3', a.getWidth()) sel = self.wire('sel') gnd = self.wire('gnd') py4hw.Constant(self, 'gnd', 0, gnd) py4hw.storage.Reg(self, 'm', aux2, gnd, aux3) py4hw.Add(self, 'add', a, aux3, aux1) py4hw.Mul(self, 'mul', aux1, c, aux2) py4hw.Bit(self, 'bit', a, 0, sel) py4hw.Mux2(self, 'mux', sel, aux1, aux2, r)
aux2 = self.wire('aux2', a.getWidth()) aux3 = self.wire('aux3', a.getWidth()) sel = self.wire('sel') gnd = self.wire('gnd') py4hw.Constant(self, 'gnd', 0, gnd) py4hw.storage.Reg(self, 'm', aux2, gnd, aux3) py4hw.Add(self, 'add', a, aux3, aux1) py4hw.Mul(self, 'mul', aux1, c, aux2) py4hw.Bit(self, 'bit', a, 0, sel) py4hw.Mux2(self, 'mux', sel, aux1, aux2, r) sys = py4hw.HWSystem() a = sys.wire('a', 8) c = sys.wire('c', 8) r = sys.wire('r', 8) obj = Circuit(sys, 'obj', a, c, r) py4hw.Constant(sys, 'a', 3, a) py4hw.Constant(sys, 'c', 3, c) py4hw.Scope(sys, 'r', r) py4hw.debug.checkIntegrity(sys) sch = py4hw.Schematic(obj)
import py4hw class Circuit(py4hw.Logic): def __init__(self, parent, name, a, b, r): super().__init__(parent, name) self.addIn('a', a) self.addIn('b', b) self.addOut('r', r) aux = self.wire('aux') py4hw.Add(self, 'add', a, b, aux) py4hw.Buf(self, 'buf', aux, r) sys = py4hw.HWSystem() a = sys.wire('a', 8) b = sys.wire('b', 8) r = sys.wire('r', 8) c = Circuit(sys, 'c', a, b, r) py4hw.Constant(sys, 'a', 3, a) py4hw.Constant(sys, 'b', 3, b) py4hw.Scope(sys, 'r', r) py4hw.debug.checkIntegrity(sys) sch = py4hw.Schematic(c)