def test_pymtl3_list_interface_views():
a = CaseBits32MsgRdyIfcOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.get_rtlir( a.in_ ) == \
rt.Array([5], rt.InterfaceView('Bits32MsgRdyIfc',
{'msg':rt.Port('output', rdt.Vector(32)), 'rdy':rt.Port('input', rdt.Vector(1))}))
def test_pymtl3_list_interface_views():
class Ifc(dsl.Interface):
def construct(s):
s.msg = dsl.OutPort(Bits32)
s.rdy = dsl.InPort(Bits1)
class A(dsl.Component):
def construct(s):
s.in_ = [Ifc() for _ in range(5)]
a = A()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.Array([5],
rt.InterfaceView('Ifc',
{'msg':rt.Port('output', rdt.Vector(32)), 'rdy':rt.Port('input', rdt.Vector(1))})) == \
rt.get_rtlir( a.in_ )
def test_pymtl3_interface_wire():
a = CaseBits32WireIfcOnly.DUT()
a.elaborate()
# in_.foo will be silently dropped!
assert rt.get_rtlir(a.in_) == rt.InterfaceView(
'Bits32FooWireBarInIfc', {'bar': rt.Port('input', rdt.Vector(32))})