def local_do_test(m): m.elaborate() rtype = rt.RTLIRGetter(cache=False).get_component_ifc_rtlir(m) ipass = VerilogVerilatorImportPass() symbols, decls = ipass.gen_signal_decl_py(rtype) assert symbols == m._ref_symbols assert decls == m._ref_decls
def DataStrategy(draw, dut): """Return a strategy that generates input vector for component `dut`.""" max_cycles = 10 ret = [] dut.elaborate() rifc = rt.RTLIRGetter(cache=False).get_component_ifc_rtlir(dut) ports = rifc.get_ports_packed() ifcs = rifc.get_ifc_views_packed() # Add reset cycle at the beginning reset1, reset2 = {}, {} for id_, port in ports: if id_ == "clk": reset1.update({id_: Bits1(0)}) reset2.update({id_: Bits1(1)}) elif id_ == "reset": reset1.update({id_: Bits1(1)}) reset2.update({id_: Bits1(1)}) else: n_dim, port_rtype = flatten(port) if port_rtype.get_direction() == "input": if n_dim: reset1.update(ArrayInitData(id_, n_dim, port_rtype)) reset2.update(ArrayInitData(id_, n_dim, port_rtype)) else: reset1.update(InPortInitData(id_, port_rtype)) reset2.update(InPortInitData(id_, port_rtype)) for id_, ifc in ifcs: n_dim, ifc_rtype = flatten(ifc) if n_dim: reset1.update(ArrayDataStrategy(id_, n_dim, ifc_rtype)) reset2.update(ArrayDataStrategy(id_, n_dim, ifc_rtype)) else: reset1.update(InterfaceInitData(id_, n_dim, ifc_rtype)) reset2.update(InterfaceInitData(id_, n_dim, ifc_rtype)) ret.append(reset1) ret.append(reset2) for i in range(max_cycles): data = {} for id_, port in ports: if id_ in ["clk", "reset"]: data.update({id_: Bits1(0)}) else: n_dim, port_rtype = flatten(port) if n_dim: if port_rtype.get_direction() == "input": data.update( draw(ArrayDataStrategy(id_, n_dim, port_rtype))) elif port_rtype.get_direction() == "input": data.update(draw(InPortDataStrategy(id_, port_rtype))) for id_, ifc in ifcs: n_dim, ifc_rtype = flatten(ifc) if n_dim: data.update(draw(ArrayDataStrategy(id_, n_dim, ifc_rtype))) else: data.update(draw(InterfaceDataStrategy(id_, ifc_rtype))) # Toggle clock signal toggle_data = {} for id_, signal in data.items(): if id_ == "clk": toggle_data.update({id_: Bits1(1)}) else: toggle_data.update({id_: copy.deepcopy(signal)}) ret.append(data) ret.append(toggle_data) return ret