示例#1
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def run_solver_bin_ar(bin_ar,
                      arch_config,
                      rtl_root,
                      run_root,
                      sim_out=None,
                      target='generic',
                      flow='vsim',
                      stdout=None,
                      stderr=None):
    global VERBOSE
    if not os.access(arch_config, os.R_OK):
        raise RuntimeError('Invalid architecture config "%s"' % arch_config)

    arch_md5 = sys_utils.md5_file(arch_config)
    cfg = read_arch_config(arch_config)
    tgt_sig = cfg.get_tgt_sig()
    sim_cc, sim_exe = sim_utils.get_rtl_tools(flow)

    sys_utils.mkdir_p(os.path.abspath(run_root))
    t_wd = get_target_out_dir(cfg.get_tgt_sig(), arch_md5, run_root)
    lib_path = os.path.join(t_wd, 'hw-libs')
    # If RTL folder does not exist, generate it from config file
    if not os.path.isdir(lib_path):
        tgt_rtl_root = os.path.join(rtl_root, 'core', cfg.name,
                                    cfg.get_tgt_attr())
        rtl_path = (os.path.join(rtl_root,
                                 'common'), os.path.join(rtl_root, 'memory'),
                    os.path.join(rtl_root, 'top'), tgt_rtl_root)
        solver_rtl_gen.generate_rtl_package(
            cfg,
            lib_path,
            rtl_path=rtl_path,
            tb_path=(os.path.join(rtl_root, 'testbench'), ),
            def_path=(os.path.join(rtl_root, 'define'), ),
            target=target,
            tb_module='simd_top_testbench',
            lib='work')
    sim_wd = os.path.join(lib_path, '%s_wd' % flow)
    # Check if it is necessary to compile the simulation libraries
    check_and_compile_solver_rtl(lib_path,
                                 sim_wd,
                                 flow,
                                 sim_cc,
                                 stdout=stdout,
                                 stderr=stderr)
    # Setup application files
    clean_solver_rtl_simulation(sim_wd)
    app_name = sys_utils.get_path_basename(bin_ar)
    setup_solver_mem_files(bin_ar, sim_wd)
    # Run the actual simulation
    run_solver_rtl_simulation(sim_exe,
                              sim_wd,
                              flow,
                              lib_path,
                              cfg,
                              stdout=stdout,
                              stderr=stderr,
                              gui=False)
    if not sim_out: sim_out = os.path.join(t_wd, 'sim-out', app_name)
    move_dump_files(sim_wd, sim_out)
示例#2
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def generate_solver_program_html(info_fpath,
                                 template_dir,
                                 out_dir,
                                 p_name=None):
    if not p_name: p_name = sys_utils.get_path_basename(info_fpath)
    p_info = solver_json_utils.read_solver_json_info(info_fpath)

    template_dir = os.path.abspath(template_dir)
    out_dir = os.path.abspath(out_dir)
    sys_utils.mkdir_p(out_dir)
    sys_utils.copy_if_newer(os.path.join(template_dir, 'css'), out_dir)
    sys_utils.copy_if_newer(os.path.join(template_dir, 'js'), out_dir)
    sys_utils.copy_if_newer(os.path.join(template_dir, 'images'), out_dir)

    funcs = sorted(p_info['functions'].items(), key=lambda x: x[1]['address'])
    dobjs = sorted(p_info['data_objects'].items(),
                   key=lambda x: x[1]['address'])
    homepage = render_template(os.path.join(template_dir, 'index.html'),
                               program_name=p_name,
                               program=p_info,
                               funcs=funcs,
                               dobjs=dobjs)
    with open(os.path.join(out_dir, 'index.html'), 'w') as f:
        f.write(homepage)
    for f in funcs:
        funcpage = render_template(os.path.join(template_dir, 'func.html'),
                                   func=f[1],
                                   funcs=funcs)
        with open(os.path.join(out_dir, 'func_%s.html' % f[1]['name']),
                  'w') as f:
            f.write(funcpage)
示例#3
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def move_dump_files(sim_wd, out_dir):
    sys_utils.mkdir_p(out_dir)
    for f in os.listdir(out_dir):
        fp = os.path.join(out_dir,f)
        if os.path.isfile(fp) and f.endswith('.dump'): os.remove(fp)
    for f in os.listdir(sim_wd):
        fp = os.path.join(sim_wd,f)
        if os.path.isfile(fp) and f.endswith('.dump'): shutil.move(fp, out_dir)
示例#4
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def move_dump_files(sim_wd, out_dir):
    sys_utils.mkdir_p(out_dir)
    for f in os.listdir(out_dir):
        fp = os.path.join(out_dir, f)
        if os.path.isfile(fp) and f.endswith('.dump'): os.remove(fp)
    for f in os.listdir(sim_wd):
        fp = os.path.join(sim_wd, f)
        if os.path.isfile(fp) and f.endswith('.dump'): shutil.move(fp, out_dir)
示例#5
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def compile_vsim_lib(compile_script, run_path, vsim='vsim',
                     stdout=None, stderr=None):
    cs = os.path.abspath(compile_script)
    if not os.access(cs, os.R_OK):
        raise RuntimeError('Invalid compilation script "%s"'%compile_script)
    cwd = os.getcwd()
    sys_utils.mkdir_p(run_path)
    os.chdir(run_path)
    try:
        if sys_utils.run_command('%s -c -do %s'%(vsim, cs),
                                 stdout=stdout, stderr=stderr):
            raise RuntimeError('Cannot compile Modelsim library')
    finally:
        os.chdir(cwd)
示例#6
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def compile_post_sim(tcsh_rc, run_dir):
    sys_utils.mkdir_p(os.path.join(run_dir, 'INCA_libs'))
    sys_utils.mkdir_p(os.path.join(run_dir, 'INCA_libs', 'worklib'))
    sys_utils.mkdir_p(os.path.join(run_dir, 'compiled'))
    sys_utils.mkdir_p(os.path.join(run_dir, 'compiled', 'work'))
    compile_cmd = os.path.join(run_dir, 'post-sim-compile.cmd')
    with open(compile_cmd) as f:
        compile_cmd = f.read()
    cmd = [
        'tcsh', '-c', 'source {0};{1};stty sane'.format(tcsh_rc, compile_cmd)
    ]
    cwd = os.getcwd()
    os.chdir(run_dir)
    try:
        if not os.path.exists('hdl.var'): open('hdl.var', 'a')
        comp_log = tempfile.TemporaryFile()
        subprocess.check_call(cmd, stdout=comp_log)
        comp_log.seek(0)
        with open('compile.log', 'w') as f:
            f.write(comp_log.read())
    except:
        print >> sys.stderr, "Unexpected error:", sys.exc_info(
        )[0], sys.exc_info()[1]
    finally:
        os.chdir(cwd)
示例#7
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def compile_iverilog_lib(filelist, run_path, inc_path, libname='work',
                         ivlog='iverilog',stdout=None, stderr=None):
    fl = os.path.abspath(filelist)
    if not os.access(fl, os.R_OK):
        raise RuntimeError('Invalid file list "%s"'%filelist)

    
    cmd = ivlog + ' -c %s -o %s'%(fl, libname)
    for p in inc_path: cmd += ' -I%s'%os.path.abspath(p)
    cwd = os.getcwd()
    sys_utils.mkdir_p(run_path)
    os.chdir(run_path)
    try:
        if sys_utils.run_command(cmd, stdout=stdout, stderr=stderr):
            raise RuntimeError('Cannot compile Icarus Verilog library')
    finally:
        os.chdir(cwd)
示例#8
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def get_target_out_dir(tgt_str, tgt_md5, p):
    d = os.path.join(p, '%s-%s'%(tgt_str, tgt_md5))
    succ = False
    cnt = 0
    while not succ:
        sys_utils.mkdir_p(d)
        tgt_sig = os.path.join(d, 'arch.sig')
        if os.path.isfile(tgt_sig):
            with open(tgt_sig) as f: sig = f.read()
            if tgt_md5 == sig: succ = True
            else:
                d = os.path.join(p, '%s-%d'%(tgt_str, cnt))
                cnt += 1
        else:
            with open(tgt_sig, 'w') as f: f.write(tgt_md5)
            succ = True
    return d
示例#9
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def compile_vsim_lib(compile_script,
                     run_path,
                     vsim='vsim',
                     stdout=None,
                     stderr=None):
    cs = os.path.abspath(compile_script)
    if not os.access(cs, os.R_OK):
        raise RuntimeError('Invalid compilation script "%s"' % compile_script)
    cwd = os.getcwd()
    sys_utils.mkdir_p(run_path)
    os.chdir(run_path)
    try:
        if sys_utils.run_command('%s -c -do %s' % (vsim, cs),
                                 stdout=stdout,
                                 stderr=stderr):
            raise RuntimeError('Cannot compile Modelsim library')
    finally:
        os.chdir(cwd)
示例#10
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def get_target_out_dir(tgt_str, tgt_md5, p):
    d = os.path.join(p, '%s-%s' % (tgt_str, tgt_md5))
    succ = False
    cnt = 0
    while not succ:
        sys_utils.mkdir_p(d)
        tgt_sig = os.path.join(d, 'arch.sig')
        if os.path.isfile(tgt_sig):
            with open(tgt_sig) as f:
                sig = f.read()
            if tgt_md5 == sig: succ = True
            else:
                d = os.path.join(p, '%s-%d' % (tgt_str, cnt))
                cnt += 1
        else:
            with open(tgt_sig, 'w') as f:
                f.write(tgt_md5)
            succ = True
    return d
示例#11
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def run_solver_bin_ar(bin_ar, arch_config, rtl_root, run_root, sim_out=None,
                      target='generic', flow='vsim', stdout=None, stderr=None):
    global VERBOSE
    if not os.access(arch_config, os.R_OK):
        raise RuntimeError('Invalid architecture config "%s"'%arch_config)

    arch_md5 = sys_utils.md5_file(arch_config)
    cfg = read_arch_config(arch_config)
    tgt_sig = cfg.get_tgt_sig()
    sim_cc, sim_exe = sim_utils.get_rtl_tools(flow)

    sys_utils.mkdir_p(os.path.abspath(run_root))
    t_wd = get_target_out_dir(cfg.get_tgt_sig(), arch_md5, run_root)
    lib_path = os.path.join(t_wd, 'hw-libs')
    # If RTL folder does not exist, generate it from config file
    if not os.path.isdir(lib_path):
        tgt_rtl_root = os.path.join(rtl_root,'core',cfg.name,cfg.get_tgt_attr())
        rtl_path = (os.path.join(rtl_root, 'common'),
                    os.path.join(rtl_root, 'memory'),
                    os.path.join(rtl_root, 'top'), tgt_rtl_root)
        solver_rtl_gen.generate_rtl_package(
            cfg, lib_path, rtl_path=rtl_path,
            tb_path  = (os.path.join(rtl_root, 'testbench'),),
            def_path = (os.path.join(rtl_root, 'define'),),
            target=target, tb_module='simd_top_testbench', lib='work')
    sim_wd = os.path.join(lib_path, '%s_wd'%flow)
    # Check if it is necessary to compile the simulation libraries
    check_and_compile_solver_rtl(lib_path, sim_wd, flow, sim_cc,
                                 stdout=stdout, stderr=stderr)
    # Setup application files
    clean_solver_rtl_simulation(sim_wd)
    app_name = sys_utils.get_path_basename(bin_ar)
    setup_solver_mem_files(bin_ar, sim_wd)
    # Run the actual simulation
    run_solver_rtl_simulation(sim_exe, sim_wd, flow, lib_path, cfg,
                              stdout=stdout, stderr=stderr, gui=False)
    if not sim_out: sim_out = os.path.join(t_wd, 'sim-out', app_name)
    move_dump_files(sim_wd, sim_out)
示例#12
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def generate_solver_program_html(info_fpath, template_dir, out_dir,
                                 p_name=None):
    if not p_name: p_name = sys_utils.get_path_basename(info_fpath)
    p_info = solver_json_utils.read_solver_json_info(info_fpath)

    template_dir = os.path.abspath(template_dir)
    out_dir = os.path.abspath(out_dir)
    sys_utils.mkdir_p(out_dir)
    sys_utils.copy_if_newer(os.path.join(template_dir, 'css'),    out_dir)
    sys_utils.copy_if_newer(os.path.join(template_dir, 'js'),     out_dir)
    sys_utils.copy_if_newer(os.path.join(template_dir, 'images'), out_dir)

    funcs = sorted(p_info['functions'].items(), key= lambda x: x[1]['address'])
    dobjs = sorted(p_info['data_objects'].items(),
                   key= lambda x: x[1]['address'])
    homepage = render_template(os.path.join(template_dir, 'index.html'),
                               program_name=p_name, program=p_info, funcs=funcs,
                               dobjs=dobjs)
    with open(os.path.join(out_dir, 'index.html'), 'w') as f: f.write(homepage)
    for f in funcs:
        funcpage = render_template(os.path.join(template_dir, 'func.html'),
                                   func=f[1], funcs=funcs)
        with open(os.path.join(out_dir, 'func_%s.html'%f[1]['name']), 'w') as f:
            f.write(funcpage)