RISC-V-Simulator

The work is a part of group project took by 4 students(including me) at IIT Ropar under the guidance of Prof. T.V. Kalyan, IIT Ropar. The aim is to create a RISC-V simulator similar to Venus( https://www.kvakil.me/venus/ ).

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
.vscode/ipch/69cdbbea29919687		.vscode/ipch/69cdbbea29919687
__pycache__		__pycache__
README.md		README.md
assemulator.py		assemulator.py
cache.py		cache.py
code.mc		code.mc
execute.py		execute.py
gui.py		gui.py
gui1.py		gui1.py
main.py		main.py
mainwindow.ui		mainwindow.ui
memory.py		memory.py
read_file.asm		read_file.asm
registers.py		registers.py
requirements.txt		requirements.txt
syntax.py		syntax.py
write_file.mc		write_file.mc

yadavAk/Assemulator_with_GUI

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RISC-V-Simulator

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