class SouthBridge(SimObject):
type = 'SouthBridge'
pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
platform = Param.Platform(Parent.any, "Platform this device is part of")
_pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
_pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave')
_cmos = Cmos(pio_addr=x86IOAddress(0x70))
_dma1 = I8237(pio_addr=x86IOAddress(0x0))
_keyboard = I8042(data_port=x86IOAddress(0x60), \
command_port=x86IOAddress(0x64))
_pit = I8254(pio_addr=x86IOAddress(0x40))
_speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
_io_apic = I82094AA(pio_addr=0xFEC00000)
# This is to make sure the interrupt lines are instantiated. Don't use
# it for anything directly.
int_lines = VectorParam.X86IntLine([], "Interrupt lines")
pic1 = Param.I8259(_pic1, "Master PIC")
pic2 = Param.I8259(_pic2, "Slave PIC")
cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
dma1 = Param.I8237(_dma1, "The first dma controller")
keyboard = Param.I8042(_keyboard, "The keyboard controller")
pit = Param.I8254(_pit, "Programmable interval timer")
speaker = Param.PcSpeaker(_speaker, "PC speaker")
io_apic = Param.I82094AA(_io_apic, "I/O APIC")
def connectPins(self, source, sink):
self.int_lines.append(X86IntLine(source=source, sink=sink))
# IDE controller
ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
ide.BAR0 = 0x1f0
ide.BAR0LegacyIO = True
ide.BAR1 = 0x3f4
ide.BAR1Size = '3B'
ide.BAR1LegacyIO = True
ide.BAR2 = 0x170
ide.BAR2LegacyIO = True
ide.BAR3 = 0x374
ide.BAR3Size = '3B'
ide.BAR3LegacyIO = True
ide.BAR4 = 1
ide.Command = 0
ide.ProgIF = 0x80
ide.InterruptLine = 14
ide.InterruptPin = 1
def attachIO(self, bus):
# Route interupt signals
self.connectPins(self.pic1.output, self.io_apic.pin(0))
self.connectPins(self.pic2.output, self.pic1.pin(2))
self.connectPins(self.cmos.int_pin, self.pic2.pin(0))
self.connectPins(self.pit.int_pin, self.pic1.pin(0))
self.connectPins(self.pit.int_pin, self.io_apic.pin(2))
# self.connectPins(self.keyboard.keyboard_int_pin,
# self.pic1.pin(1))
self.connectPins(self.keyboard.keyboard_int_pin, self.io_apic.pin(1))
# self.connectPins(self.keyboard.mouse_int_pin,
# self.pic2.pin(4))
self.connectPins(self.keyboard.mouse_int_pin, self.io_apic.pin(12))
# Tell the devices about each other
self.pic1.slave = self.pic2
self.speaker.i8254 = self.pit
self.io_apic.external_int_pic = self.pic1
# Connect to the bus
self.cmos.pio = bus.port
self.dma1.pio = bus.port
self.ide.pio = bus.port
self.keyboard.pio = bus.port
self.pic1.pio = bus.port
self.pic2.pio = bus.port
self.pit.pio = bus.port
self.speaker.pio = bus.port
self.io_apic.pio = bus.port
self.io_apic.int_port = bus.port
class SouthBridge(SimObject):
type = 'SouthBridge'
cxx_header = "dev/x86/south_bridge.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of")
_pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
_pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave')
_cmos = Cmos(pio_addr=x86IOAddress(0x70))
_dma1 = I8237(pio_addr=x86IOAddress(0x0))
_keyboard = I8042(data_port=x86IOAddress(0x60), \
command_port=x86IOAddress(0x64))
_pit = I8254(pio_addr=x86IOAddress(0x40))
_speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
_io_apic = I82094AA(pio_addr=0xFEC00000)
pic1 = Param.I8259(_pic1, "Master PIC")
pic2 = Param.I8259(_pic2, "Slave PIC")
cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
dma1 = Param.I8237(_dma1, "The first dma controller")
keyboard = Param.I8042(_keyboard, "The keyboard controller")
pit = Param.I8254(_pit, "Programmable interval timer")
speaker = Param.PcSpeaker(_speaker, "PC speaker")
io_apic = Param.I82094AA(_io_apic, "I/O APIC")
# IDE controller
ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
ide.BAR0 = 0x1f0
ide.BAR0LegacyIO = True
ide.BAR1 = 0x3f4
ide.BAR1Size = '3B'
ide.BAR1LegacyIO = True
ide.BAR2 = 0x170
ide.BAR2LegacyIO = True
ide.BAR3 = 0x374
ide.BAR3Size = '3B'
ide.BAR3LegacyIO = True
ide.BAR4 = 1
ide.Command = 0
ide.ProgIF = 0x80
ide.InterruptLine = 14
ide.InterruptPin = 1
def attachIO(self, bus, dma_ports):
# Route interupt signals
self.int_lines = \
[X86IntLine(source=self.pic1.output, sink=self.io_apic.pin(0)),
X86IntLine(source=self.pic2.output, sink=self.pic1.pin(2)),
X86IntLine(source=self.cmos.int_pin, sink=self.pic2.pin(0)),
X86IntLine(source=self.pit.int_pin, sink=self.pic1.pin(0)),
X86IntLine(source=self.pit.int_pin, sink=self.io_apic.pin(2)),
X86IntLine(source=self.keyboard.keyboard_int_pin,
sink=self.io_apic.pin(1)),
X86IntLine(source=self.keyboard.mouse_int_pin,
sink=self.io_apic.pin(12))]
# Tell the devices about each other
self.pic1.slave = self.pic2
self.speaker.i8254 = self.pit
self.io_apic.external_int_pic = self.pic1
# Connect to the bus
self.cmos.pio = bus.master
self.dma1.pio = bus.master
self.ide.pio = bus.master
self.ide.config = bus.master
if dma_ports.count(self.ide.dma) == 0:
self.ide.dma = bus.slave
self.keyboard.pio = bus.master
self.pic1.pio = bus.master
self.pic2.pio = bus.master
self.pit.pio = bus.master
self.speaker.pio = bus.master
self.io_apic.pio = bus.master
self.io_apic.int_master = bus.slave
class PARDg5VICH(Bridge):
type = 'PARDg5VICH'
cxx_header = "dev/cellx/ich.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of")
# PARDg5VICHCP Control Plane
cp = Param.PARDg5VICHCP(PARDg5VICHCP(), "Control plane for PARDg5-V ICH")
# ICH interface logic
remapper = PARDg5VICHRemapper()
xbar = NoncoherentXBar()
ranges = [
AddrRange(x86IOAddress(0), size=0x400),
AddrRange(0xFEC00000, size=0x14)
]
#
# Internal Chipsets: CMOS, I/O APIC, PIT*4, UART*4
#
_cmos = Cmos(pio_addr=x86IOAddress(0x70))
_io_apic = I82094AX(pio_addr=0xFEC00000)
_pits = [
I8254(pio_addr=x86IOAddress(0x40)),
I8254(pio_addr=x86IOAddress(0x44)),
I8254(pio_addr=x86IOAddress(0x48)),
I8254(pio_addr=x86IOAddress(0x4C))
]
_serials = [
I8250X(pio_addr=x86IOAddress(0x3f8), terminal=Terminal()),
I8250X(pio_addr=x86IOAddress(0x2f8), terminal=Terminal()),
I8250X(pio_addr=x86IOAddress(0x3e8), terminal=Terminal()),
I8250X(pio_addr=x86IOAddress(0x2e8), terminal=Terminal())
]
cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
io_apic = Param.I82094AX(_io_apic, "I/O APIC")
pits = VectorParam.I8254(_pits, "Programmable interval timer")
serials = VectorParam.I8250X(_serials, "Serial port and terminal")
# "Non-existant" devices
fake_devices = [
# I8237 DMA
IsaFake(pio_addr=x86IOAddress(0x0)),
# I8259 PIC
IsaFake(pio_addr=x86IOAddress(0x20), pio_size=2), # Master PIC
IsaFake(pio_addr=x86IOAddress(0xA0), pio_size=2), # Slave PIC
# I8042 Keyboard/Mouse Controller
IsaFake(pio_addr=x86IOAddress(0x60), pio_size=1), # data
IsaFake(pio_addr=x86IOAddress(0x64), pio_size=1), # cmd
# PcSpeaker
IsaFake(pio_addr=x86IOAddress(0x61), pio_size=1),
# "Non-existant" ports used for timing purposes by the linux kernel
IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1), # i_dont_exist1
IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1), # i_dont_exist2
# IDE controller
IsaFake(pio_addr=x86IOAddress(0x3f4), pio_size=3), # BAR0
IsaFake(pio_addr=x86IOAddress(0x170), pio_size=8), # BAR1
IsaFake(pio_addr=x86IOAddress(0x374), pio_size=3), # BAR2
# A device to catch accesses to the non-existant floppy controller.
IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
]
def attachIO(self, bus, dma_ports):
# Route interupt signals
self.int_lines = [
X86IntLine(source=self.pits[0].int_pin, sink=self.io_apic.pin(0)),
X86IntLine(source=self.pits[1].int_pin, sink=self.io_apic.pin(1)),
X86IntLine(source=self.pits[2].int_pin, sink=self.io_apic.pin(2)),
X86IntLine(source=self.pits[3].int_pin, sink=self.io_apic.pin(3)),
X86IntLine(source=self.serials[0].int_pin,
sink=self.io_apic.pin(4)),
X86IntLine(source=self.serials[1].int_pin,
sink=self.io_apic.pin(5)),
X86IntLine(source=self.serials[2].int_pin,
sink=self.io_apic.pin(6)),
X86IntLine(source=self.serials[3].int_pin,
sink=self.io_apic.pin(7)),
X86IntLine(source=self.cmos[0].int_pin, sink=self.io_apic.pin(8))
]
# connect internal devices
self.io_apic.pio = self.xbar.master
devices = [self.cmos] + self.pits + self.serials + self.fake_devices
for dev in devices:
dev.pio = self.xbar.master
# connect I/O APIC int master to the bus
self.io_apic.int_master = bus.slave
# connect ICH to the bus
bus.master = self.slave
self.master = self.remapper.slave
self.remapper.master = self.xbar.slave