def performOp(self, aluop, s1, s2, setFlags=False):
outputBus = Bus(s1.size)
zero = [1]
if (aluop == AND):
for i in range(s1.size):
newBit = s1.at(i) and s2.at(i)
if (newBit and zero):
zero[0] = 0
outputBus.set(i, newBit)
i -= 1
elif (aluop == ORR):
for i in range(s1.size):
newBit = s1.at(i) or s2.at(i)
if (newBit and zero):
zero[0] = 0
outputBus.set(i, newBit)
i -= 1
elif (aluop == ADD):
outputBus, zero[0] = self.add(s1, s2)
elif (aluop == SUB):
outputBus, zero[0] = self.add(s1, self.TwosComp(s2))
elif (aluop == PASSSB):
outputBus = s2
for i in range(s2.size):
if (s2.at(i)):
zero[0] = 0
break
else:
print("Error with aluop")
zero[0] = 0
return outputBus, zero[0]
def shiftImm(self, imm): newImm = Bus(64) newImm.set(0, 0) newImm.set(1, 0) i = 2 while(i < 64): newImm.set(i, imm.at(i-2)) i += 1 return newImm
def performOp(self, signop, Imm26):
extBit = []
extensionIndex = []
outputBus = Bus(64)
if (signop == ITYPE):
extBit.append(0)
i = 10
j = 0
extensionIndex.append(12)
while (i <= 21):
outputBus.set(j, Imm26.at(i))
i += 1
j += 1
elif (signop == DTYPE):
extBit.append(Imm26.at(20))
i = 12
j = 0
extensionIndex.append(9)
while (i <= 20):
outputBus.set(j, Imm26.at(i))
i += 1
j += 1
elif (signop == CBTYPE):
extBit.append(Imm26.at(23))
i = 5
j = 0
extensionIndex.append(19)
while (i <= 23):
outputBus.set(j, Imm26.at(i))
i += 1
j += 1
elif (signop == BTYPE):
extBit.append(Imm26.at(25))
i = 0
extensionIndex.append(25)
while (i <= 25):
outputBus.set(i, Imm26.at(i))
i += 1
else:
print("Error in sign extender")
i = extensionIndex[0]
while (i < 64):
outputBus.set(i, extBit[0])
i += 1
return outputBus
def TwosComp(self, source):
one = Bus(source.size)
invertedSource = Bus(source.size)
for i in range(source.size):
invertedSource.set(i, not source.at(i))
if (i == 0):
one.set(0, 1)
else:
one.set(i, 0)
outputBus, trash = self.add(invertedSource, one)
return outputBus
return (Bus(64), Bus(64))
else:
return1 = self.file[locToIndex(loc1)]
return2 = self.file[locToIndex(loc2)]
return (return1, return2)
def printRegFile(self, format=''):
for i in range(self.width):
print('[', i, '] ', sep='', end='')
self.file[i].print(format)
if __name__ == '__main__':
rf = RegisterFile(8)
rf.printRegFile('x')
bus = Bus(0, [
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1
])
loc = Bus(4)
loc.set(2, 1)
print()
rf.performOp(1, Bus(4), Bus(4), loc, bus)
trash, newBus = rf.performOp(0, Bus(4), loc, Bus(4), Bus(64))
newBus.print('x')
def add(self, s1, s2):
cin = 0
outputBus = Bus(s1.size)
zero = 1
for i in range(s1.size):
bit1 = s1.at(i)
bit2 = s2.at(i)
if (bit1 and bit2):
if (cin):
outputBus.set(i, 1)
cin = 1
zero = 0
else:
outputBus.set(i, 0)
cin = 1
elif ((bit1 and not bit2) or (not bit1 and bit2)):
if (cin):
outputBus.set(i, 0)
cin = 1
else:
outputBus.set(i, 1)
cin = 0
zero = 0
else:
if (cin):
outputBus.set(i, 1)
cin = 0
zero = 0
else:
outputBus.set(i, 0)
cin = 0
return outputBus, zero