def rundecam():
readline.set_completer_delims(' \t\n;')
readline.parse_and_bind("tab: complete")
readline.set_completer(cmmd_and_path_complete)
parser = argparse.ArgumentParser(
usage='python EC [-h] <orac.v> <cam.v> <solu.v>',
description=
'This program will check the correntness for corresponding solution',
)
parser.add_argument(
'<orac.v>',
help=
'input oracle Verilog file that defines the function of the circuit')
parser.add_argument('<cam.v>',
help='the camouflaged circuit that we want to solve.')
parser.add_argument('<solu.v>', help='the solutiion try to proof')
orcIn = sys.argv[1]
OracInPath = os.path.abspath(orcIn)
if not os.path.isfile(OracInPath):
print 'Invalid oracle circuit file!!!!\n'
return
camIn = sys.argv[2]
CamInPath = os.path.abspath(camIn)
if not os.path.isfile(CamInPath):
print 'Invalid camouflaged circuit file!!!!\n'
return
soluIn = sys.argv[3]
SoluInPath = os.path.abspath(soluIn)
if not os.path.isfile(CamInPath):
print 'Invalid solution file!!!!\n'
return
res = EC(OracInPath, CamInPath, SoluInPath)
if res == 1:
print "Solution is correct!"
elif res == 0:
print "Solution is wrong!"
else:
print "BUG!"
print 'Thank you!\n'
]
with open("time_info_original", "a") as outfile:
outfile.write("#Number of gate #BASE\n")
# run simp and it will generate the finalsolu and iterationinfo
for i in cam_list:
cmmd = "/usr/bin/time -v -o temp-time ./minisat-incre-simp decam-incre c1908-abcmap-fmt.v " + i
call(cmmd, shell=True)
# rename iterationinfo
os.rename("increIterationInfo.log", i.strip(".v") + "-interationInfo.dat")
# check EC and import to a txt
res = EC("c1908-abcmap-fmt.v", i, "finalSolu.log")
if (res == 1):
content = "Circuit: " + i + " is CORRECT!\n"
elif (res == 0):
content = "Circuit: " + i + " is WRONG!\n"
else:
content = "Circuit: " + i + " is BUG!\n"
with open("EC_result.txt", "a") as output:
output.write(content)
with open("time_info_original", "a") as outfile:
outfile.write(
i.strip("c1908-mux4-").strip(".v") + " ")
with open("temp-time", "r") as infile:
timeline = infile.read().split("\n")
with open("time_info_original", "a") as outfile:
outfile.write("#Number of gate #BASE\n")
# run simp and it will generate the finalsolu and iterationinfo
for i in cam_list:
cmmd = "/usr/bin/time -v -o temp-time ./minisat-incre-simp decam-incre c499-abcmap-fmt.v " + i
call(cmmd, shell = True)
# rename iterationinfo
os.rename("increIterationInfo.log", i.strip(".v") + "-interationInfo.dat")
# check EC and import to a txt
res = EC("c499-abcmap-fmt.v", i, "finalSolu.log")
if (res == 1):
content = "Circuit: " + i + " is CORRECT!\n"
elif (res == 0):
content = "Circuit: " + i + " is WRONG!\n"
else:
content = "Circuit: " + i + " is BUG!\n"
with open("EC_result.txt", "a") as output:
output.write(content)
with open("time_info_original", "a") as outfile:
outfile.write(i.strip("c499-mux4-").strip(".v") + " ")
with open("temp-time", "r") as infile:
timeline = infile.read().split("\n")
for line in timeline:
outfile.write(
"#Num_mux #Num_XOR #Runtime\n")
while (1):
for Num_mux in range(1, 53):
Mux_circuit = "c7552-mux4-" + str(Num_mux) + ".v"
XOR_circuit = "c7552-mux4-" + str(Num_mux) + "-XOR-" + str(
210 - Num_mux * 4) + ".v"
make_cmmd = "python XOR_Cam_random.py " + Mux_circuit + " " + str(
210 - Num_mux * 4)
call(make_cmmd, shell=True)
# run
run_cmmd = "/usr/bin/time -v -o temp-time ./minisat-incre-simp decam-incre c7552-abcmap-fmt.v " + XOR_circuit
call(run_cmmd, shell=True)
#os.rename("increIterationInfo.log", XOR_circuit.strip(".v") + "-interationInfo.dat")
# EC
res = EC("c7552-abcmap-fmt.v", XOR_circuit, "finalSolu.log")
if (res == 1):
content = "Circuit: " + XOR_circuit + " is CORRECT!\n"
elif (res == 0):
content = "Circuit: " + XOR_circuit + " is WRONG!\n"
else:
content = "Circuit: " + XOR_circuit + " is BUG!\n"
with open("EC_result.txt", "a") as output:
output.write(content)
# collect data
with open("temp-time", "r") as infile:
timeline = infile.read().split("\n")
for line in timeline:
if "User time (seconds):" in line:
time_info = line.replace("User time (seconds):", "")
with open("atime_info_WIRE", "a") as outfile:
outfile.write(str(j) + "\t")
# create file
for iteration in range(1, 11):
make_cmmd = " python DummyWire.py c432-abcmap-fmt.v " + str(j)
call(make_cmmd, shell=True)
cmmd = "/usr/bin/time -v -o atemp-time ./minisat-incre-simp decam-incre c432-abcmap-fmt.v " + i
call(cmmd, shell=True)
# rename iterationinfo
os.rename("increIterationInfo.log",
i.strip(".v") + "-interationInfo.dat")
# check EC and import to a txt
res = EC("c432-abcmap-fmt.v", i, "finalSolu.log")
if (res == 1):
content = "Circuit: " + i + " is CORRECT!\n"
elif (res == 0):
content = "Circuit: " + i + " is WRONG!\n"
else:
content = "Circuit: " + i + " is BUG!\n"
with open("aEC_result.txt", "a") as output:
output.write(content)
with open("atemp-time", "r") as infile:
timeline = infile.read().split("\n")
for line in timeline:
if "User time (seconds):" in line:
time_info = line.replace("User time (seconds):", "")
]
with open("time_info_original", "a") as outfile:
outfile.write("#Number of gate #BASE\n")
# run simp and it will generate the finalsolu and iterationinfo
for i in cam_list:
cmmd = "/usr/bin/time -v -o temp-time ./minisat-incre-simp decam-incre c3540-abcmap-fmt.v " + i
call(cmmd, shell=True)
# rename iterationinfo
os.rename("increIterationInfo.log", i.strip(".v") + "-interationInfo.dat")
# check EC and import to a txt
res = EC("c3540-abcmap-fmt.v", i, "finalSolu.log")
if (res == 1):
content = "Circuit: " + i + " is CORRECT!\n"
elif (res == 0):
content = "Circuit: " + i + " is WRONG!\n"
else:
content = "Circuit: " + i + " is BUG!\n"
with open("EC_result.txt", "a") as output:
output.write(content)
with open("time_info_original", "a") as outfile:
outfile.write(
i.strip("c3540-mux4-").strip(".v") + " ")
with open("temp-time", "r") as infile:
timeline = infile.read().split("\n")
def rundecam():
readline.set_completer_delims(' \t\n;')
readline.parse_and_bind("tab: complete")
readline.set_completer(cmmd_and_path_complete)
print "\n\t########## Welcome to SAT SLOVER system. ##########"
print "\t#This system is used to solve the camouflaged ckt #"
print "\t#reverse engineering problem. #"
print "\t###################################################"
print "\n\tThis program dissects circuit and finds the correct"
print "\tinternal components. User needs to inform the number"
print "\tof obfuscated gates in the circuit. The program now c-"
print "\t-onsiders 3 choices for each obfuscated gate by default.\n"
parser = argparse.ArgumentParser(
usage=
'python decam-v5-cmmdline.py [-h] <orac.v> <cam.v> [-forbid][-o <res_file>]',
description=
'This program will use orac.v and cam.v to generate a programming bit vector (if exists)\
that can make the cam.v has the same function as orac.v. The results and solution are presented in the\
output file.',
)
parser.add_argument(
'<orac.v>',
help=
'input oracle Verilog file that defines the function of the circuit')
parser.add_argument('<cam.v>',
help='the camouflaged circuit that we want to solve.')
parser.add_argument('--forbid',
action='append',
type=str,
help='define the forbidden programming bits for MUX')
parser.add_argument('-o',
"--res_file",
nargs='?',
type=argparse.FileType('w'),
help='output file which stores iteration times.')
args = parser.parse_args()
outfile = args.res_file
print 'The forbid bits are : %s' % args.forbid
forbid_bits = args.forbid
orcIn = sys.argv[1]
OracInPath = os.path.abspath(orcIn)
if not os.path.isfile(OracInPath):
print 'Invalid oracle circuit file!!!!\n'
return
camIn = sys.argv[2]
CamInPath = os.path.abspath(camIn)
if not os.path.isfile(CamInPath):
print 'Invalid camouflaged circuit file!!!!\n'
return
#obfGateNum = raw_input('>>> ')
#obfGateNum = int(obfGateNum)
totTime1 = time.time()
if outfile == None:
verbose = False
else:
verbose = True
mainClass = DissectCkt(OracInPath, CamInPath, forbid_bits, verbose)
if verbose == True:
res = mainClass.main()
else:
mainClass.main()
res = ""
totTime2 = time.time()
totTime = round(totTime2 - totTime1, 4)
line4 = 'The total time used (including file parse time) is\n'
line5 = str(totTime) + ' s\n'
res += line4
res += line5
if verbose == True:
outfile.write(res)
outfile.close()
print 'Result is written in', os.path.abspath(
outfile.name) #b/c 'outfile' is a file object
else:
print res
# Here I add EC #
findSoluFilelog = re.search(r'(.*)(?=\.)',
CamInPath).group() + '-_findSolu' + '.log'
res = EC(OracInPath, CamInPath, findSoluFilelog)
if res == 1:
print "Solution found!"
elif res == 0:
print "System is malfunction!"
else:
print "BUG!"
print 'Thank you!\n'
]
with open("time_info_original", "a") as outfile:
outfile.write("#Number of gate #BASE\n")
# run simp and it will generate the finalsolu and iterationinfo
for i in cam_list:
cmmd = "/usr/bin/time -v -o temp-time ./minisat-incre-simp decam-incre c5315-abcmap-fmt.v " + i
call(cmmd, shell=True)
# rename iterationinfo
os.rename("increIterationInfo.log", i.strip(".v") + "-interationInfo.dat")
# check EC and import to a txt
res = EC("c5315-abcmap-fmt.v", i, "finalSolu.log")
if (res == 1):
content = "Circuit: " + i + " is CORRECT!\n"
elif (res == 0):
content = "Circuit: " + i + " is WRONG!\n"
else:
content = "Circuit: " + i + " is BUG!\n"
with open("EC_result.txt", "a") as output:
output.write(content)
with open("time_info_original", "a") as outfile:
outfile.write(
i.strip("c5315-mux4-").strip(".v") + " ")
with open("temp-time", "r") as infile:
timeline = infile.read().split("\n")
]
with open("time_info_original", "a") as outfile:
outfile.write("#Number of gate #BASE\n")
# run simp and it will generate the finalsolu and iterationinfo
for i in cam_list:
cmmd = "/usr/bin/time -v -o temp-time ./minisat-incre-simp decam-incre c7552-abcmap-fmt.v " + i
call(cmmd, shell=True)
# rename iterationinfo
os.rename("increIterationInfo.log", i.strip(".v") + "-interationInfo.dat")
# check EC and import to a txt
res = EC("c7552-abcmap-fmt.v", i, "finalSolu.log")
if (res == 1):
content = "Circuit: " + i + " is CORRECT!\n"
elif (res == 0):
content = "Circuit: " + i + " is WRONG!\n"
else:
content = "Circuit: " + i + " is BUG!\n"
with open("EC_result.txt", "a") as output:
output.write(content)
with open("time_info_original", "a") as outfile:
outfile.write(
i.strip("c7552-mux4-").strip(".v") + " ")
with open("temp-time", "r") as infile:
timeline = infile.read().split("\n")