track = pm.set_variable('20um')
gap = pm.set_variable('10um', name='gap')
track_big = pm.set_variable('25um')
gap_big = pm.set_variable('15um')
track_middle = pm.set_variable('22.5um')
gap_middle = pm.set_variable('12.5um')
offset = pm.set_variable('-50um')
# chip2
with chip2(['0.5mm', '0.5mm'], [1, 0]):
port0, = elt.create_port(
chip2, [track, track + 2 * gap],
name='port0') # default is the widths of track and gap
with chip2(['1.0mm', '0.1mm'], [-1, 0]):
port1, = elt.create_port(
chip2, name='port1') # default is the widths of track and gap
with chip2(['2.0mm', '0.1mm'], [-1, 0]):
port2, = elt.create_port(
chip2, [track, track + 2 * gap],
name='port2') # default is the widths of track and gap
chip2.draw_cable(port0,
port1,
port2,
is_bond=False,
fillet='200um',
track = pm.set_variable("20um")
gap = pm.set_variable("10um", name="gap")
track_big = pm.set_variable("25um")
gap_big = pm.set_variable("15um")
track_middle = pm.set_variable("22.5um")
gap_middle = pm.set_variable("12.5um")
offset = pm.set_variable("-50um")
# chip2
with chip2(["0.5mm", "0.5mm"], [1, 0]):
(port0, ) = elt.create_port(
chip2, [track, track + 2 * gap],
name="port0") # default is the widths of track and gap
with chip2(["1.0mm", "0.1mm"], [-1, 0]):
(port1, ) = elt.create_port(
chip2, name="port1") # default is the widths of track and gap
with chip2(["2.0mm", "0.1mm"], [-1, 0]):
(port2, ) = elt.create_port(
chip2, [track, track + 2 * gap],
name="port2") # default is the widths of track and gap
chip2.draw_cable(
port0,
port1,
port2,
is_bond=False,
track = pm.set_variable('20um')
gap = pm.set_variable('10um', name='gap')
track_big = pm.set_variable('25um')
gap_big = pm.set_variable('15um')
track_middle = pm.set_variable('22.5um')
gap_middle = pm.set_variable('12.5um')
offset = pm.set_variable('-50um')
# chip1
# default is the widths of track and gap
port11, = elt.create_port(chip1, [track, track + 2 * gap], name="port11")
with chip1(['2.0mm', '0.0mm'], [1, 0]):
# default is the widths of track and gap
port12, = elt.create_port(chip1, [track, track + 2 * gap], name="port12")
bond_length, bond_slope, pcb_track, pcb_gap = '200um', 0.5, '300um', '200um'
with chip1(['0.5mm', '0.5mm'], [0, 1]):
con_port1, = elt.draw_connector(chip1,
track,
gap,
bond_length,
pcb_track,
pcb_gap,
0.5,